公开(公告)号：US20080008964A1

公开(公告)日：2008-01-10

申请号：US11309168

申请日：2006-07-05

Applicant: Chia-Hua Chan ,  Jen-Inn Chyi ,  Chang-Chi Pan ,  Chii-Chang Chen

Inventor： Chia-Hua Chan ,  Jen-Inn Chyi ,  Chang-Chi Pan ,  Chii-Chang Chen

IPC: B05D5/00 ,  G11B7/24

CPC classification number: H01L33/22 ,  H01L33/0062

Abstract: A method of fabricating a nano/micro structure comprising the following steps is provided. First, a film is provided and then a mixed material comprising a plurality of particles and a filler among the particles is formed on the film. Next, the particles are removed by the etching process, the solvent extraction process or the like, such that a plurality of concaves is formed on the surface of the filler, which serves as a nano/micro structure of the film.

Abstract translation: 提供一种制造纳米/微结构的方法，包括以下步骤。 首先，提供膜，然后在膜上形成包含颗粒中的多个颗粒和填料的混合材料。 接下来，通过蚀刻工艺，溶剂萃取工艺等去除颗粒，使得在作为膜的纳米/微结构的填料的表面上形成多个凹部。

公开(公告)号：US20050224813A1

公开(公告)日：2005-10-13

申请号：US10815091

申请日：2004-03-31

Applicant: Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

Inventor： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

IPC: B41J2/12 ,  H01L25/075 ,  H01L33/50

CPC classification number: H01L33/507 ,  H01L25/0756 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device comprises a light-emitting unit including a plurality of first connecting pads, a base substrate including a plurality of second connecting pads, and a plurality of conductive bumps that connect the first connecting pads of the light-emitting unit to the second connecting pads of the base substrate. In the manufacturing process, a reflow process is performed to bond the conductive bumps to the first and second connecting pads. The light-emitting unit is configured to emit a first light radiation upon the application of an electric current flow, and the base substrate is configured to emit a second light radiation when stimulated by the first light radiation.

Abstract translation: 发光装置包括：发光单元，包括多个第一连接焊盘;基板，包括多个第二连接焊盘;以及多个导电凸块，其将所述发光单元的第一连接焊盘连接到 基底基板的第二连接焊盘。 在制造过程中，执行回流处理以将导电凸块接合到第一和第二连接焊盘。 发光单元被配置为在施加电流时发射第一光辐射，并且基底基板被配置为当被第一光辐射刺激时发射第二光辐射。

公开(公告)号：US20050224812A1

公开(公告)日：2005-10-13

申请号：US10814872

申请日：2004-03-31

Applicant: Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

Inventor： Yu-Chuan Liu ,  Chia-Ming Lee ,  I-Ling Chen ,  Jen-Inn Chyi

IPC: H01L27/15 ,  H01L33/32 ,  H01L33/40 ,  H01L33/42 ,  H01L33/50

CPC classification number: H01L33/508 ,  H01L33/32 ,  H01L33/40 ,  H01L33/42 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A light-emitting device includes a multi-layer structure configured to emit a first light radiation, and a cap layer covering a surface area of the multi-layer structure while leaving exposed electrode areas defined thereon, wherein the cap layer is made of a material capable of emitting at least one second light radiation when stimulated by the first light radiation. The cap layer, being made of a material blend incorporating a passivation material and a luminescent material compound, is coated on the multi-layer structure.

Abstract translation: 发光器件包括被配置为发射第一光辐射的多层结构，以及覆盖多层结构的表面区域同时留下限定在其上的暴露的电极区域的覆盖层，其中，盖层由材料制成 能够在被第一光辐射刺激时发射至少一个第二光辐射。 覆盖层由包含钝化材料和发光材料化合物的材料混合物制成，涂覆在多层结构上。

公开(公告)号：US06881602B2

公开(公告)日：2005-04-19

申请号：US10410989

申请日：2003-04-08

Applicant: Chia-Ming Lee ,  Jen-Inn Chyi

Inventor： Chia-Ming Lee ,  Jen-Inn Chyi

IPC: H01L33/00 ,  H01L33/02 ,  H01L33/14 ,  H01L21/00

CPC classification number: H01L33/025 ,  H01L33/0016 ,  H01L33/02 ,  H01L33/14

Abstract: According to a preferred embodiment of the present invention, there is provided a novel and optimal semiconductor light emitting device comprising a substrate, an n layer disposed co-extensively on the substrate, an n++ layer disposed non-extensively and flush on one side of the n layer. Furthermore, a p+ layer is disposed co-extensively on the n++ layer of the LED according to the invention, with a p layer further disposed co-extensively on the p+ layer. A p cladding layer is disposed co-extensively on the p layer. A multiple quantum well (MQW) layer is disposed co-extensively on the p cladding layer, and an n cladding layer is further disposed co-extensively on the MQW layer. A second n layer is disposed co-extensively on the n cladding layer. An n+ layer is disposed co-extensively on the second n layer of the LED according to the invention. After partially etching the device, an n electrode is formed opposite n++ layer non-extensively on the surface of n layer, and a second n electrode is formed non-extensively (without etching) upon the n+ layer.

Abstract translation: 根据本发明的优选实施例，提供了一种新颖且最佳的半导体发光器件，其包括基底，共同设置在基底上的n层，设置非基底层的n + 在n层的一侧上非常平滑地冲洗。 此外，根据本发明，将ap + +层共同地布置在LED的n + ++层上，其中ap层进一步同时布置在p < SUP> + 层。 p包层共同设置在p层上。 多量子阱（MQW）层共同设置在p包覆层上，并且n包覆层进一步同时布置在MQW层上。 第n层被共同设置在n包层上。 根据本发明，n + SUP层被共同地布置在LED的第二n层上。 在部分蚀刻该器件之后，在n层的表面上非常广泛地形成n电极，并且在n层上形成第二n电极（非蚀刻） ^{+ 层。}

公开(公告)号：US06309895B1

公开(公告)日：2001-10-30

申请号：US09237662

申请日：1999-01-27

Applicant: Cheng-Chung Jaing ,  Jyh-Shin Chen ,  Jen-Inn Chyi ,  Jeng-Jiing Sheu

Inventor： Cheng-Chung Jaing ,  Jyh-Shin Chen ,  Jen-Inn Chyi ,  Jeng-Jiing Sheu

IPC: H01G706

CPC classification number: H01L28/56 ,  C23C14/088 ,  H01L28/60 ,  H01L28/75

Abstract: A preparation for forming a thin film capacitor includes forming an amorphous ferroelectric film, such as barium strontium titanate [(Ba,Sr)TiO3] film, for use as an interface between a metal electrode and a polycrystalline ferroelectric film, such as (Ba,Sr) TiO3 film. The polycrystalline ferroelectric film serves as a dielectric layer of the thin film capacitor in view of the fact that the polycrystalline ferroelectric film has a high dielectric constant. The amorphous ferroelectric film serves as a buffer layer for inhibiting the leakage current of the thin film capacitor. The amorphous ferroelectric film is grown by sputtering and by introducing a working gas, such as argon, and a reactive gas, such as oxygen, into a reaction chamber in which a plasma is generated at room temperature.

Abstract translation: 用于形成薄膜电容器的制备包括：形成诸如钛酸锶钡[（Ba，Sr）TiO 3]膜的非晶铁电体膜，用作金属电极和多晶铁电体膜之间的界面，例如（Ba， Sr）TiO3膜。 鉴于多晶强电介质膜具有高介电常数的事实，多晶铁电体膜用作薄膜电容器的电介质层。 非晶铁电体膜用作抑制薄膜电容器的漏电流的缓冲层。 通过溅射和诸如氩的工作气体和诸如氧的反应性气体引入到在室温下产生等离子体的反应室中生长非晶铁电膜。

公开(公告)号：US08586995B2

公开(公告)日：2013-11-19

申请号：US13571041

申请日：2012-08-09

Applicant: Jen-Inn Chyi ,  Geng-Yen Lee ,  Hsueh-Hsing Liu

Inventor： Jen-Inn Chyi ,  Geng-Yen Lee ,  Hsueh-Hsing Liu

IPC: H01L29/205 ,  H01L29/78

CPC classification number: H01L29/66212 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/475 ,  H01L29/7787 ,  H01L29/872

Abstract: A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.

Abstract translation: 具有高击穿电压的半导体元件包括衬底，缓冲层，半导体复合层和偏置电极。 设置在基板上的缓冲层包括高边缘位错缺陷密度区域。 设置在缓冲层上的半导体复合层包括由于第一高边缘位错缺陷密度区域而形成的第二高边缘位错缺陷密度区域。 偏置电极设置在半导体复合层上。 由于第一和第二高边缘位错缺陷密度区域产生缺陷能级捕获电子的虚拟栅极效应，使得在半导体复合层处形成从偏置电极扩展的扩展的耗尽区。 当偏置电极接收到反向偏压时，扩展耗尽区减小漏电流并增加半导体元件的击穿电压。

公开(公告)号：US20120329254A1

公开(公告)日：2012-12-27

申请号：US13595797

申请日：2012-08-27

Applicant: Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

Inventor： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC: H01L21/20

CPC classification number: H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract translation: 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US20120328234A1

公开(公告)日：2012-12-27

申请号：US13293228

申请日：2011-11-10

Applicant: Hung-Chih Lu ,  Jen-Inn Chyi

Inventor： Hung-Chih Lu ,  Jen-Inn Chyi

IPC: G02B6/125

CPC classification number: G02B6/124 ,  G02B6/1228

Abstract: A low-loss optical coupling apparatus includes a silicon-on-insulator wafer, a silicon dioxide layer, a taper waveguide, a channel waveguide and a thick-film silicon dioxide layer. The silicon-on-insulator wafer is formed with a silicon substrate. The silicon dioxide layer is provided on the silicon substrate. The taper waveguide comprises a slab region formed on the silicon dioxide layer and a waveguide region formed on the slab region. An end of a chip is connected to an end of the waveguide region. The channel waveguide is formed on the slab region and connected to another end of the waveguide region. The thick-film silicon dioxide layer extends on the taper waveguide and covers the entire waveguide region.

Abstract translation: 低损耗光耦合装置包括绝缘体上硅晶片，二氧化硅层，锥形波导，通道波导和厚膜二氧化硅层。 绝缘体上硅晶片由硅衬底形成。 二氧化硅层设置在硅衬底上。 锥形波导包括形成在二氧化硅层上的平板区域和形成在板区域上的波导区域。 芯片的一端连接到波导区域的一端。 通道波导形成在平板区域上，并连接到波导区域的另一端。 厚膜二氧化硅层在锥形波导上延伸并覆盖整个波导区域。

公开(公告)号：US20110272719A1

公开(公告)日：2011-11-10

申请号：US12776834

申请日：2010-05-10

Applicant: Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

Inventor： Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

IPC: H01L33/32

CPC classification number: H01L33/14 ,  H01L33/04

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1.

Abstract translation: 本发明公开了一种LED结构，其中N型电流扩展层插入在N型半导体层之间以均匀地分布流过N型半导体层的电流。 N型电流扩展层包括从低带隙到较高带隙的顺序堆叠的至少三个子层，其中具有较低带隙的子层在衬底附近，并且子层 具有较高带隙的发光层靠近发光层。 N型电流扩展层的每个子层由通式In x Al y Ga（1-x-y）N表示，其中0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1和0＆nlE; x + y＆nlE;

公开(公告)号：US08048786B2

公开(公告)日：2011-11-01

申请号：US12263555

申请日：2008-11-03

Applicant: Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

Inventor： Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

IPC: H01L21/20

CPC classification number: H01L21/0237 ,  C30B25/02 ,  C30B25/18 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.

Abstract translation: 本发明提供一种制造含有氮化镓（GaN）的单晶衬底的方法，包括以下步骤。 首先，在主体基板上形成多个含有GaN的岛。 接下来，使用包含GaN的多个岛作为掩模来蚀刻衬底并形成不均匀的主体衬底。 然后，在不均匀的主体衬底上进行外延，使含有GaN的岛尺寸增长并且合并成含有GaN的连续单晶膜。 最后，从不均匀的主体衬底上分离含有GaN的单晶膜，得到含有GaN的单晶衬底。 根据本发明，可以节省加工时间，提高成品率。