公开(公告)号：US08237174B2

公开(公告)日：2012-08-07

申请号：US12776834

申请日：2010-05-10

申请人： Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

发明人： Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

IPC分类号： H01L27/15 ,  H01L31/12 ,  H01L33/00

CPC分类号： H01L33/14 ,  H01L33/04

摘要： The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1.

摘要翻译： 本发明公开了一种LED结构，其中N型电流扩展层插入在N型半导体层之间以均匀地分布流过N型半导体层的电流。 N型电流扩展层包括从低带隙到较高带隙的顺序堆叠的至少三个子层，其中具有较低带隙的子层在衬底附近，并且子层 具有较高带隙的发光层靠近发光层。 N型电流扩展层的每个子层由通式In x Al y Ga（1-x-y）N表示，其中0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1和0＆nlE; x + y＆nlE;

公开(公告)号：US20110272719A1

公开(公告)日：2011-11-10

申请号：US12776834

申请日：2010-05-10

申请人： Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

发明人： Peng-Ren Chen ,  Hsueh-Hsing Liu ,  Jen-Inn Chyi

IPC分类号： H01L33/32

CPC分类号： H01L33/14 ,  H01L33/04

摘要： The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1.

摘要翻译： 本发明公开了一种LED结构，其中N型电流扩展层插入在N型半导体层之间以均匀地分布流过N型半导体层的电流。 N型电流扩展层包括从低带隙到较高带隙的顺序堆叠的至少三个子层，其中具有较低带隙的子层在衬底附近，并且子层 具有较高带隙的发光层靠近发光层。 N型电流扩展层的每个子层由通式In x Al y Ga（1-x-y）N表示，其中0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1和0＆nlE; x + y＆nlE;

公开(公告)号：US08524583B2

公开(公告)日：2013-09-03

申请号：US13177330

申请日：2011-07-06

申请人： Jen-Inn Chyi ,  Hsueh-Hsing Liu ,  Hsien Yu Lin

发明人： Jen-Inn Chyi ,  Hsueh-Hsing Liu ,  Hsien Yu Lin

IPC分类号： H01L21/205

CPC分类号： H01L21/02639 ,  C30B23/025 ,  C30B23/04 ,  C30B25/04 ,  C30B25/186 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/16 ,  H01L33/20

摘要： A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate, each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.

摘要翻译： 用于生长半极性氮化物的方法包括以下步骤：在硅衬底上形成多个平行的离散沟槽，每个离散的沟槽具有第一壁和第二壁，其中在硅衬底的表面和第一壁之间形成倾斜角 壁; 在所述硅衬底和所述沟槽上形成缓冲层，其中所述第一壁上的所述缓冲层在所述生长区中具有多个生长区和多个非生长区，并与所述生长区互补; 在缓冲层上形成覆盖层并露出生长区; 以及从缓冲层的生长区域生长半极性氮化物并覆盖覆盖层。 由此，硅衬底和半极性氮化物之间的热应力引起的裂纹减少，并且提高了半极性氮化物膜的质量。

公开(公告)号：US08586995B2

公开(公告)日：2013-11-19

申请号：US13571041

申请日：2012-08-09

申请人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Hsueh-Hsing Liu

发明人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Hsueh-Hsing Liu

IPC分类号： H01L29/205 ,  H01L29/78

CPC分类号： H01L29/66212 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/475 ,  H01L29/7787 ,  H01L29/872

摘要： A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.

摘要翻译： 具有高击穿电压的半导体元件包括衬底，缓冲层，半导体复合层和偏置电极。 设置在基板上的缓冲层包括高边缘位错缺陷密度区域。 设置在缓冲层上的半导体复合层包括由于第一高边缘位错缺陷密度区域而形成的第二高边缘位错缺陷密度区域。 偏置电极设置在半导体复合层上。 由于第一和第二高边缘位错缺陷密度区域产生缺陷能级捕获电子的虚拟栅极效应，使得在半导体复合层处形成从偏置电极扩展的扩展的耗尽区。 当偏置电极接收到反向偏压时，扩展耗尽区减小漏电流并增加半导体元件的击穿电压。

公开(公告)号：US08048786B2

公开(公告)日：2011-11-01

申请号：US12263555

申请日：2008-11-03

申请人： Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

发明人： Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

IPC分类号： H01L21/20

CPC分类号： H01L21/0237 ,  C30B25/02 ,  C30B25/18 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

摘要： The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.

摘要翻译： 本发明提供一种制造含有氮化镓（GaN）的单晶衬底的方法，包括以下步骤。 首先，在主体基板上形成多个含有GaN的岛。 接下来，使用包含GaN的多个岛作为掩模来蚀刻衬底并形成不均匀的主体衬底。 然后，在不均匀的主体衬底上进行外延，使含有GaN的岛尺寸增长并且合并成含有GaN的连续单晶膜。 最后，从不均匀的主体衬底上分离含有GaN的单晶膜，得到含有GaN的单晶衬底。 根据本发明，可以节省加工时间，提高成品率。

公开(公告)号：US20100068872A1

公开(公告)日：2010-03-18

申请号：US12263555

申请日：2008-11-03

申请人： Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

发明人： Jen-Inn Chyi ,  Guan-Ting Chen ,  Hsueh-Hsing Liu

IPC分类号： H01L21/205

CPC分类号： H01L21/0237 ,  C30B25/02 ,  C30B25/18 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265

摘要： The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.

摘要翻译： 本发明提供一种制造含有氮化镓（GaN）的单晶衬底的方法，包括以下步骤。 首先，在主体基板上形成多个含有GaN的岛。 接下来，使用包含GaN的多个岛作为掩模来蚀刻衬底并形成不均匀的主体衬底。 然后，在不平坦的主体衬底上进行外延，使含有GaN的岛尺寸增长并且合并成含有GaN的连续单晶膜。 最后，从不均匀的主体衬底上分离含有GaN的单晶膜，得到含有GaN的单晶衬底。 根据本发明，可以节省加工时间，提高成品率。

公开(公告)号：US08629012B2

公开(公告)日：2014-01-14

申请号：US13595797

申请日：2012-08-27

申请人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L21/338

CPC分类号： H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

摘要翻译： 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US08478091B2

公开(公告)日：2013-07-02

申请号：US13106072

申请日：2011-05-12

申请人： Hung-Chih Lu ,  Jen-Inn Chyi

发明人： Hung-Chih Lu ,  Jen-Inn Chyi

IPC分类号： G02B6/34

CPC分类号： G02B6/29353

摘要： A single-stage 1×5 grating-assisted wavelength division multiplexer is provided. A grating-assisted asymmetric Mach-Zehnder interferometer, a plurality of grating-assisted cross-state directional couplers and a plurality of novel side-band eliminators are combined to form the multiplexer. Only general gratings are required, not Bragg grating, for 5-channel wavelength division multiplexing in a single stage. A nearly ideal square-like band-pass filtering passband is obtained. The present disclosure can be used as a core device in IC-to-IC optical interconnects for multiplexing and demultiplexing of an optical transceiver. The present disclosure has a small size and good performance.

摘要翻译： 提供单级1×5光栅辅助波分复用器。 组合光栅辅助非对称马赫 - 策德尔干涉仪，多个光栅辅助交叉状态定向耦合器和多个新型侧带消除器以形成多路复用器。 只需要一般光栅，而不是布拉格光栅，用于单级5通道波分复用。 获得几乎理想的方形带通滤波通带。 本公开可以用作用于复用和解复用光收发器的IC至IC光互连中的核心设备。 本公开具有小尺寸和良好的性能。

公开(公告)号：US08426226B2

公开(公告)日：2013-04-23

申请号：US13342431

申请日：2012-01-03

申请人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

发明人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

IPC分类号： H01L21/00

CPC分类号： H01L27/15

摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.

摘要翻译： 一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。 由此，肖特基二极管经由金属层与LED电连接。 从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

公开(公告)号：US08101447B2

公开(公告)日：2012-01-24

申请号：US11961478

申请日：2007-12-20

申请人： Hung-Cheng Lin ,  Chia-Ming Lee ,  Jen-Inn Chyi

发明人： Hung-Cheng Lin ,  Chia-Ming Lee ,  Jen-Inn Chyi

IPC分类号： H01L33/20

CPC分类号： H01L33/10 ,  H01L33/20

摘要： The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.

摘要翻译： 本发明公开了一种发光二极管（LED）元件及其制造方法，其可以提高LED的光提取效率，其中蚀刻基板以获得具有倾斜的自然晶体面的池，并且LED外延结构选择性地 形成在盆地内。 由此，得到具有多个倾斜的LED元件。 通过倾斜，全内反射的概率降低，LED的光提取效率得到提升。