公开(公告)号：US07356632B2

公开(公告)日：2008-04-08

申请号：US11402700

申请日：2006-04-11

申请人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

发明人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

IPC分类号： G06F13/14 ,  G06F12/00 ,  G06F1/32

CPC分类号： G06F13/1668 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

摘要翻译： 本发明提供一种支持数据总线反转的数据存储控制器。 从存储器发送的数据被接收在芯片组中，其进一步将数据发送到数据处理装置。 在接收存储器数据的同时，芯片组将带宽加倍并降低频率，使得处理数据的时间裕度增加。 此外，在向数据处理装置输出数据之后，将第一帧数据与总线空闲状态进行比较，以进一步降低数据反转和功耗的频率。

公开(公告)号：US07231560B2

公开(公告)日：2007-06-12

申请号：US10985461

申请日：2004-11-10

申请人： Jiin Lai ,  Wayne Tseng

发明人： Jiin Lai ,  Wayne Tseng

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31716 ,  G01R31/043 ,  G01R31/2815

摘要： This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.

摘要翻译： 本发明公开了一种用于测试与板载PCI Express设备相关联的母板上的至少一个物理链路的方法。 测试卡连接到母板上的输入/输出端口，其中测试卡具有PCI Express测试设备。 测试模式从测试卡发送到PCI Express设备，并通过测试卡从PCI Express设备通过物理链路接收测试结果模式，以进行测试。 检查测试结果模式，以确定主板上物理链路的缺陷。

公开(公告)号：US20060232290A1

公开(公告)日：2006-10-19

申请号：US11131401

申请日：2005-05-18

申请人： Hung Kuo ,  Jenny Chen ,  Jiin Lai

发明人： Hung Kuo ,  Jenny Chen ,  Jiin Lai

IPC分类号： G01R31/02

CPC分类号： G01R19/16552

摘要： A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.

摘要翻译： 电压监测电路能够集成到芯片中并监测电压质量。 它主要使用第一个波形器接收要测量的电压源的电压信号，将其处理为逻辑信号，并输出到第一逻辑电平变压器。 第一数字信号通过处理变换，并且可以由寄存器记录，使得管理系统可以通过总线读取寄存器的内容，以进一步确定电压源是否具有电压浪涌的情况。 类似地，逆变器可以连接在第二波形与第二逻辑电平变换器之间，以监测电压源是否具有欠电流脉冲。 这样，可以实现利用简单模拟电路的组合来监视芯片中的电压质量的目的。

公开(公告)号：US07082489B2

公开(公告)日：2006-07-25

申请号：US10172332

申请日：2002-06-14

申请人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

发明人： Bi-Yun Yeh ,  Jiin Lai ,  Sheng-Chung Wu

IPC分类号： G06F13/14 ,  G06F12/00 ,  G06F1/32

CPC分类号： G06F13/1668 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

公开(公告)号：US20060095633A1

公开(公告)日：2006-05-04

申请号：US11257260

申请日：2005-10-24

申请人： Ruei-Ling Lin ,  Jiin Lai

发明人： Ruei-Ling Lin ,  Jiin Lai

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/4208 ,  G06F2213/0024

摘要： A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission bandwidth or bus transmission speed.

摘要翻译： 在计算机系统的中央处理单元和桥接芯片之间使用数据传输协调方法。 通过将计算机系统进入协调状态，执行数据传输协调方法。 通过桥芯片和CPU通过相互之间的最大位数，以经由前端总线进行数据传输。 然后，可以根据第一和第二最大比特数来协调CPU和桥接芯片之间用于数据传输的通用可操作的最大比特数。 一旦确定了通用可操作的最大位数，则CPU被复位以通常可操作的最大位数进行操作。 最大位数是总线传输带宽或总线传输速度的位数。

公开(公告)号：US06948057B2

公开(公告)日：2005-09-20

申请号：US10114519

申请日：2002-04-02

申请人： Jiin Lai ,  Jih-Hsin Tsai ,  Hsiang-I Huang

发明人： Jiin Lai ,  Jih-Hsin Tsai ,  Hsiang-I Huang

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F9/4401

摘要： A memory module storing therein boot codes, a core logic device capable of distinguishing such memory module from the other memory modules of the same module specification, and a method for realizing the boot codes from the memory module storing therein the boot codes are disclosed. All the memory modules are electrically connected to the core logic device via respective signal pins, but the memory module storing therein boot codes outputs an identifying signal different from the identifying signals outputted by the other memory modules in a booting process. Therefore, the core logic device can locate the memory module storing therein the boot codes, and the host device can accomplish the booting process by reading the boot codes from the specific memory module.

摘要翻译： 存储有引导代码的存储器模块，能够将这种存储器模块与相同模块规格的其他存储器模块区分开的核心逻辑器件，以及用于从其中存储引导代码的存储器模块中实现引导代码的方法。 所有存储器模块经由相应的信号引脚电连接到核心逻辑器件，但存储器模块中存储有引导代码，在引导过程中输出与其他存储器模块输出的识别信号不同的识别信号。 因此，核心逻辑设备可以定位其中存储引导代码的存储器模块，并且主机设备可以通过从特定存储器模块读取引导代码来完成启动过程。

公开(公告)号：US06941398B2

公开(公告)日：2005-09-06

申请号：US09826784

申请日：2001-04-04

申请人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Min-Hung Chen ,  Meng-Cheng Ku ,  Huei-Li Chou

发明人： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Min-Hung Chen ,  Meng-Cheng Ku ,  Huei-Li Chou

IPC分类号： G06F13/24 ,  G06F13/14

CPC分类号： G06F13/24 ,  G06F2213/2418

摘要： A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

摘要翻译： 一种处理方法，芯片组和用于支持消息信号中断的控制器。 监视PCI总线上的存储器写事务。 当在写事务的中断消息中指定的系统存储器的地址位于保留的中断地址的范围时，执行中断服务序列。 保留的中断地址位于系统存储器的地址中。 因此，要处理的数据和系统指定的消息被写入缓冲器中并且按顺序排列。 解决了“写缓冲区延迟”的问题，与PCI总线的级别无关。 许多系统指定的消息可以存储在系统存储器中，从而可以在相同的中断服务程序中处理来自不同外设组件的多个系统消息信号中断。

公开(公告)号：US20050039083A1

公开(公告)日：2005-02-17

申请号：US10954509

申请日：2004-09-29

申请人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G06F7/58 ,  G06F11/00 ,  G06F11/26 ,  G06F11/263

CPC分类号： G06F11/261 ,  G06F11/263

摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

摘要翻译： 提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。 在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。 这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。 在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。

公开(公告)号：US06571323B2

公开(公告)日：2003-05-27

申请号：US10115780

申请日：2002-04-03

申请人： Jiin Lai ,  Chih-kuo Kao

发明人： Jiin Lai ,  Chih-kuo Kao

IPC分类号： G06F1200

CPC分类号： G06F12/0895 ,  G06F12/0215 ,  G06F12/123

摘要： A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

公开(公告)号：US06233528B1

公开(公告)日：2001-05-15

申请号：US09148949

申请日：1998-09-08

申请人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

发明人： Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin

IPC分类号： G01R1300

CPC分类号： G01R31/31709 ,  G01R31/3016

摘要： A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.

摘要翻译： 与用于测试第一信号和第二信号的测试仪一起使用的信号测试装置包括接收第一信号的选择信号发生器和用于产生当第一信号和第二信号处于特定状态时其状态改变的选择信号的第二信号 以及信号选择器，用于响应于所选择的信号状态选择性地输出第一和第二信号之一。 本发明还提供了一种信号测试方法，包括以下步骤：a）响应于第一信号和第二信号产生具有多个脉冲的选定信号，b）获得两个相邻时间之间的多个时间差 各个脉冲分别达到特定电压，c）在两个相邻的相应时间差之间获得多个绝对值，以及d）通过将绝对值的平均值除以2来获得相位差。