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    Semiconductor memory device
    35.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080159037A1

    公开(公告)日：2008-07-03

    申请号：US12004291

    申请日：2007-12-20

    Applicant: Jong-Cheol Lee ,  Myeong-O Kim

    Inventor： Jong-Cheol Lee ,  Myeong-O Kim

    IPC: G11C7/08

    CPC classification number: G11C7/08 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

    Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

    Abstract translation: 一种半导体存储器件，包括位线读出放大器，用于放大与存储在存储单元的电容器中的电荷相对应的电压并输出放大电压;以及I / O读出放大器，用于接收位线读出放大器的输出，放大 公开了输出的电压电平并输出放大的电压电平。 半导体存储器件包括读出放大使能信号控制部分，其接收初始读出放大使能信号，将初始读出放大使能信号顺序地延迟多个预定时间周期，并且选择性地输出多个延迟读出放大使能信号， 半导体存储器件的操作速度和制造成品率; 多个时钟读出放大器，其各自接收I / O读出放大器的输出信号，响应于多个延迟读出放大使能信号中的每一个放大I / O读出放大器的输出信号，并依次输出输出 电源电压信号或接地电压电平响应; 以及前级输出驱动电路，其依次接收多个时钟读出放大器的输出信号，将多个时钟读出放大器的输出信号延迟预定的时间周期，然后截取时钟感测放大器的输出 前一步。

    SENSE AMPLIFIER CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    36.
    发明申请
    SENSE AMPLIFIER CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件的感测放大器电路及其操作方法

    公开(公告)号：US20080151664A1

    公开(公告)日：2008-06-26

    申请号：US11830142

    申请日：2007-07-30

    Applicant: Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

    Inventor： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

    IPC: G11C7/00

    CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C2207/005

    Abstract: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

    Abstract translation: 半导体存储器件的读出放大器电路及其操作方法，其中读出放大器电路包括与位线连接的位线读出放大器，以检测和放大位线的信号，校准电路校准 基于位线读出放大器的逻辑阈值的位线的电压电平。 位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。 位线读出放大器可以包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。 校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。

    Semiconductor memory device and method of manufacturing the semiconductor memory device
    39.
    发明申请
    Semiconductor memory device and method of manufacturing the semiconductor memory device 有权
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US20060138523A1

    公开(公告)日：2006-06-29

    申请号：US11311143

    申请日：2005-12-20

    Applicant: Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    Inventor： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    IPC: H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

    Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

    Abstract translation: 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。

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