公开(公告)号：US07257329B2

公开(公告)日：2007-08-14

申请号：US10378096

申请日：2003-02-28

Applicant: Kameran Azadet ,  Fadi Ryad Olivier Saibi

Inventor： Kameran Azadet ,  Fadi Ryad Olivier Saibi

IPC: H04B10/04 ,  H04B10/12

CPC classification number: H04B10/2507 ,  H04B10/5167

Abstract: A duobinary optical communication system is disclosed that employs pulse amplitude modulation (PAM) techniques to provide further improvements in spectral efficiency. A disclosed PAM duobinary optical transmitter converts a plurality of input bits to an N level signal using PAM techniques; adds a current N level signal to a previous N level signal to produce a 2N−1 level signal; and converts the 2N−1 level signal to an optical signal for transmission to a receiver. A disclosed PAM duobinary optical receiver detects a power level of the received optical signal (encoded using pulse amplitude modulation and duobinary encoding techniques to encode a plurality of bits) and maps the detected power level to a plurality of bits to return the transmitted information. An exemplary PAM-4 duobinary optical communication system combines PAM-4 modulation techniques with duobinary pulse shaping techniques to provide an overall factor of four improvement in spectral efficiency by reducing the bandwidth of the optical signal.

Abstract translation: 公开了使用脉冲幅度调制（PAM）技术来提供频谱效率的进一步改进的双二进制光通信系统。 公开的PAM双向光发射机使用PAM技术将多个输入比特转换成N电平信号; 将当前N电平信号添加到先前的N电平信号以产生2N-1电平信号; 并将2N-1电平信号转换成光信号以发送到接收机。 所公开的PAM双二进制光接收机检测接收到的光信号的功率电平（使用脉冲幅度调制和双二进制编码技术编码多个比特），并将检测到的功率电平映射到多个比特以返回发送的信息。 示例性的PAM-4双二进制光通信系统将PAM-4调制技术与双二进制脉冲整形技术相结合，通过降低光信号的带宽来提供频谱效率的四个改进的总体因素。

公开(公告)号：US20070025490A1

公开(公告)日：2007-02-01

申请号：US11191895

申请日：2005-07-28

Applicant: Kameran Azadet ,  Fuji Yang

Inventor： Kameran Azadet ,  Fuji Yang

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/093 ,  H03L7/0995 ,  H03L2207/50

Abstract: Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

Abstract translation: 本发明的实施例包括包括锁相环（PLL）的集成电路。 集成电路包括相位检测器，频率检测器，环路滤波器，数字控制振荡器和相应的多个分频器。 相位检测器基于参考时钟信号与多个时钟相位输入的相位比较来产生第一二进制输出。 频率检测器基于参考时钟信号与时钟相位输入的频率比较产生第二二进制输出。 环路滤波器基于第一个二进制输出和第二个二进制输出产生第三个二进制输出。 基于第三个二进制输出，DCO通过分频器将时钟相位输入反馈到相位检测器，并且基于第三个二进制输出将一个时钟相位反馈到频率检测器。

公开(公告)号：US20060064755A1

公开(公告)日：2006-03-23

申请号：US10945663

申请日：2004-09-21

Applicant: Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

Inventor： Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

IPC: G06F12/14

CPC classification number: H04L63/145 ,  G06F21/564 ,  G06F21/566

Abstract: A virus detection mechanism is described in which virus detection is provided by a network integrated protection (NIP) adapter. The NIP adapter checks incoming media data prior to it being activated by a computing device. The NIP adapter operates independently of a host processor to receive information packets from a network. This attribute of independence allows NIP anti-virus (AV) techniques to be “always on” scanning incoming messages and data transfers. By being independent of but closely coupled to the host processor, complex detection techniques, such as using check summing or pattern matching, can be efficiently implemented on the NIP adapter without involving central processor resources and time consuming mass storage accesses. The NIP adapter may be further enhanced with a unique fading memory (FM) facility to allow for a flexible and economical implementation of polymorphic virus detection.

Abstract translation: 描述了病毒检测机制，其中病毒检测由网络集成保护（NIP）适配器提供。 NIP适配器在计算设备激活之前检查传入的媒体数据。 NIP适配器独立于主机处理器操作以从网络接收信息分组。 这种独立性允许NIP防病毒（AV）技术“永远在”扫描传入的消息和数据传输。 通过独立于主机处理器紧密耦合，可以在NIP适配器上有效地实现诸如使用校验和或模式匹配的复杂检测技术，而不涉及中央处理器资源和耗时的大容量存储访问。 NIP适配器可以通过独特的衰落存储器（FM）设施进一步增强，以允许灵活和经济地实施多态性病毒检测。

公开(公告)号：US20050114721A1

公开(公告)日：2005-05-26

申请号：US10874834

申请日：2004-06-23

Applicant: Kameran Azadet ,  Leilei Song

Inventor： Kameran Azadet ,  Leilei Song

IPC: H02J13/00 ,  H04B1/16 ,  H04B7/26 ,  H04L29/00 ,  H04Q9/00 ,  G06F1/26

CPC classification number: H04W52/0277 ,  Y02D70/142

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract translation: 公开了一种用于电子设备的电源管理的方法和装置。 本发明通过在电池电平降低时通过选择具有降低的功耗的传输模式来降低通过网络进行通信的电子设备的功耗。 公开的电源管理过程监视电子设备的电池电量，并且当电池功率电平达到一个或多个预定阈值电平时，选择具有较低功耗的传输模式（例如，传输速率）。

公开(公告)号：US09176735B2

公开(公告)日：2015-11-03

申请号：US12324926

申请日：2008-11-28

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F7/483 ,  G06F9/30 ,  G06F17/16

CPC classification number: G06F9/3001

Abstract: Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.

Abstract translation: 为具有具有一个或多个非线性复合函数的指令集的数字信号处理器提供了方法和装置。 为处理器提供了一种方法。 从程序获得一个或多个非线性复杂软件指令。 非线性复杂软件指令具有至少一个复数作为输入。 一个或多个非线性复函数从预定义的指令集应用到至少一个复数。 产生由一个复数或两个实数组成的输出。 功能单元可以实现一个或多个非线性复合函数。 在一个实施例中，公开了一种处理由多个复数组成的复矢量的基于矢量的数字信号处理器。 处理器可以并行处理多个复数。

公开(公告)号：US09128790B2

公开(公告)日：2015-09-08

申请号：US12362879

申请日：2009-01-30

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F1/035 ,  G06F7/556

CPC classification number: G06F7/556 ,  G06F1/035 ,  G06F2101/10

Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.

Abstract translation: 提供了一种数字信号处理器，其具有使用缩减的查找表的具有指数函数的指令集。 所公开的数字信号处理器通过将输入值x分解为整数部分N来估算输入值x的指数函数，N，大于指定值x0的第一小数部分q1，以及第二分数 部分，q2，小于指定值x0; 使用多项式近似计算2q2，例如立方近似; 从查表中获得2q1; 并且通过将2q2,2q1和2N相乘来估计输入值x的指数函数。 查找表条目具有比输入值x中的位数少的位数。

公开(公告)号：US09069686B2

公开(公告)日：2015-06-30

申请号：US12324931

申请日：2008-11-28

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F17/17 ,  G06F17/10 ,  G06F1/035 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F17/10 ,  G06F1/035 ,  G06F9/3001 ,  G06F9/383

Abstract: A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function.

Abstract translation: 公开了一种数字信号处理器和方法，其具有使用减小尺寸和指数级变化的步长的查找表的具有一个或多个非线性函数的指令集。 数字信号处理器通过从近似于值x的非线性函数的至少一个查找表中获得至少两个值来评估值x的非线性函数，其中至少一个外观 -up表使用指数变化的步长存储用于非线性函数的值的子集; 并且内插所述至少两个获得的值以获得结果y。 值x中的前导零的位置可以用作至少一个查找表中的索引。 内插可以包括例如线性内插或多项式插值。 对于周期性非线性函数可以可选地使用模运算。

公开(公告)号：US09069685B2

公开(公告)日：2015-06-30

申请号：US12324927

申请日：2008-11-28

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F17/17 ,  G06F17/10 ,  G06F1/035 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F17/10 ,  G06F1/035 ,  G06F9/3001 ,  G06F9/383

Abstract: A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function.

Abstract translation: 公开了一种使用具有缩小尺寸的查找表的具有一个或多个非线性函数的指令集的数字信号处理器和方法。 数字信号处理器通过从至少一个查找表获得接近值x的非线性函数的两个或更多个值来评估值x的非线性函数，其中至少一个 查找表存储非线性函数的值的子集; 并且内插两个或更多获得的值以获得结果y。 插值可以包括例如线性内插或多项式插值。 在另一变型中，可以对周期性非线性函数采用模运算。

公开(公告)号：US20140108477A1

公开(公告)日：2014-04-17

申请号：US13701376

申请日：2012-10-26

Applicant: Kameran Azadet ,  Meng-Lin Yu ,  Joseph H. Othmer ,  Joseph Williams ,  Albert Molina

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Joseph H. Othmer ,  Joseph Williams ,  Albert Molina

IPC: G06F5/01

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract translation: 提供了具有具有向量卷积函数的指令集的向量处理器。 所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括Ni样本; 以及通过Ni系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。 矢量处理器例如响应于具有矢量输入的一个或多个向量卷积软件指令来执行该方法。 矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。

公开(公告)号：US08595604B2

公开(公告)日：2013-11-26

申请号：US13247439

申请日：2011-09-28

Applicant: Samer Hijazi ,  Carl Murray ,  Joseph H. Othmer ,  Albert Molina ,  Kameran Azadet

Inventor： Samer Hijazi ,  Carl Murray ,  Joseph H. Othmer ,  Albert Molina ,  Kameran Azadet

IPC: H03M13/00

CPC classification number: H03M13/451 ,  H03M13/13 ,  H03M13/6502

Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

Abstract translation: 提供基于搜索范围的线性块解码器。 通过计算对应于接收向量v的校正子向量S来解码接收向量v， （S = vH）; 获得对应于所计算的校正子向量S的所有可能的误差向量集合，其中所有可能的误差向量集合e从预先计算的误差表获得并且具有指定的最大数量的比特错误; 基于所接收的向量v和所有可能的误差向量的集合e来计算所有可能的接收向量x的集合; 确定最接近接收矢量的k位码矢量，v; 以及确定与所述k位码矢量x相关联的n位数据矢量d。 可以通过将所有可能的误差向量乘以综合征矩阵来产生预计算误差表，以获得与所有可能的误差向量相关联的所有可能的校正子向量。