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    Method of Manufacturing Non-Volatile Memory Device
    33.
    发明申请
    Method of Manufacturing Non-Volatile Memory Device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20080090353A1

    公开(公告)日：2008-04-17

    申请号：US11859618

    申请日：2007-09-21

    Applicant: Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

    Inventor： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: A method of manufacturing a non-volatie memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

    Abstract translation: 制造非挥发性记忆装置的方法包括在基板上形成隧道绝缘层，在隧道绝缘层上形成导电图案，在导电图案上形成下介电层，进行第一热处理工艺以密度较低 并且形成具有比第一经热处理的下电介质层上的下介电层的能带隙小的能带隙的中间电介质层。 该方法还包括形成上介电层，其包括与中间介电层上的下电介质层的材料基本相同的材料，执行第二热处理工艺以使中介电层和上电介质层致密并形成导电层 第二热处理的上介电层。

    High performance MIS capacitor with HfO2 dielectric
    36.
    发明授权
    High performance MIS capacitor with HfO2 dielectric 失效
    具有HfO2电介质的高性能MIS电容器

    公开(公告)号：US07094712B2

    公开(公告)日：2006-08-22

    申请号：US10793818

    申请日：2004-03-08

    Applicant: Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

    Inventor： Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

    IPC: H01L21/31

    CPC classification number: H01L21/0228 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: Disclosed is a method for forming metal oxide dielectric layers, more particularly HfO2 dielectric layers, using an atomic layer deposition (ALD) method in which a series of thin intermediate layers are formed and treated with one or more oxidizers and nitrogents before the next intermediate layer is formed on the substrate. The intermediate oxidation treatments reduce the number of organic contaminants incorporated into the metal oxide layer from the organometallic precursors to produce a dielectric layer having improved current leakage characteristics. The dielectric layers formed in this manner remain susceptible to crystallization if exposed to temperatures much above 550° C., so subsequent semiconductor manufacturing processes should be modified or eliminated to avoid such temperatures or limit the duration at such temperatures to maintain the performance of the dielectric materials.

    Abstract translation: 公开了一种使用原子层沉积（ALD）方法形成金属氧化物电介质层，更具体地是HfO 2 电介质层的方法，其中形成一系列薄的中间层并用一个或多个 在下一个中间层之前形成氧化剂和氮。 中间氧化处理减少了从有机金属前体引入到金属氧化物层中的有机污染物的数量，以产生具有改善的电流泄漏特性的电介质层。 如果暴露在高于550℃的温度下，以这种方式形成的电介质层仍然易于结晶，因此随后的半导体制造工艺应当被修改或消除以避免这种温度或限制在这样的温度下的持续时间以保持电介质的性能 材料

    Method for manufacturing semiconductor device employing dielectric layer used to form conductive layer into three dimensional shape
    39.
    发明授权
    Method for manufacturing semiconductor device employing dielectric layer used to form conductive layer into three dimensional shape 有权
    使用用于将导电层形成三维形状的电介质层制造半导体器件的方法

    公开(公告)号：US06689696B2

    公开(公告)日：2004-02-10

    申请号：US09939723

    申请日：2001-08-28

    Applicant: Joo-won Lee ,  Ki-yeon Park

    Inventor： Joo-won Lee ,  Ki-yeon Park

    IPC: H01L21311

    CPC classification number: H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/31625 ,  H01L28/91

    Abstract: A method for manufacturing a semiconductor device employing a dielectric layer for forming a conductive layer into a three-dimensional shape. The dielectric layer is formed on a substrate in such a manner as to provide an intrinsic etch rate within the layer which increases in the direction of the thickness or depth of the dielectric layer. This variable intrinsic etch rate within the dielectric layer is achieved by changing one of a plurality of deposition variables. Once formed, the dielectric layer is selectively etched to form a through hole to contact a conductive area underlying the dielectric layer. A conductive layer is formed in the through hole, which may be a storage node of a capacitor.

    Abstract translation: 一种制造半导体器件的方法，该半导体器件采用将导电层形成三维形状的电介质层。 电介质层以这样一种方式形成在衬底上，以提供层内的固有蚀刻速率，其在电介质层的厚度或深度的方向上增加。 通过改变多个沉积变量之一来实现电介质层内的该可变本征蚀刻速率。 一旦形成，就选择性地蚀刻电介质层以形成通孔以接触介电层下面的导电区域。 在通孔中形成导电层，该导电层可以是电容器的存储节点。

    ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS
    40.
    发明申请
    ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS 审中-公开
    包括氧化物介质和界面层的电子器件

    公开(公告)号：US20140327062A1

    公开(公告)日：2014-11-06

    申请号：US14073354

    申请日：2013-11-06

    Applicant: Ki-Yeon PARK ,  Hyun-Jun Kim ,  Se-Hyoung Ahn ,  Young-Geun Park ,  Ki-Vin Im

    Inventor： Ki-Yeon PARK ,  Hyun-Jun Kim ,  Se-Hyoung Ahn ,  Young-Geun Park ,  Ki-Vin Im

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10808 ,  H01L27/1085 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/517

    Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.

    Abstract translation: 电子器件可以包括衬底，衬底上的氧化物介电层，氧化物介电层上的界面层和界面层上的电极。 氧化物介电层可以包括在第一和第二氧化锆层之间的氧化铝层。 界面层可以具有第一形成焓，并且氧化物介电层可以在衬底和界面层之间。 电极可具有比第一形成焓高的第二形成焓，并且界面层可以在氧化物介电层和电极之间。

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