公开(公告)号：US20100264458A1

公开(公告)日：2010-10-21

申请号：US12747099

申请日：2009-01-27

Applicant: Ionut Radu ,  Oleg Kononchuk ,  Konstantin Bourdelle

Inventor： Ionut Radu ,  Oleg Kononchuk ,  Konstantin Bourdelle

IPC: H01L29/02 ,  H01L21/26 ,  H01L21/71

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/76256

Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Abstract translation: 一种用于电子，光学或光电子领域应用的异质结构的方法。 该方法包括在施主基板或接收器基板之一或两个基板上提供厚度小于或等于25纳米的氧化硅层，在900℃下热处理含有氧化硅层的基板 在含有氩或氢中的至少一种的中性或还原性气氛下，在至少1200℃，以在氧化硅内部形成层捕获通孔，在与氧化硅层的接合界面处将基板粘合在一起， 定位在它们之间，通过在25℃至500℃下退火衬底来加强接合，使得在接合界面处保留气体种类的捕获孔，并将作为施主衬底的一部分的活性层转移到接收器衬底上 以获得异质结构。

公开(公告)号：US07767545B2

公开(公告)日：2010-08-03

申请号：US11910104

申请日：2006-03-29

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/46 ,  H01L21/04

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694

Abstract: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method.

Abstract translation: 一种用于制造具有第一材料的顶层和其晶格参数不同于第一材料的第二材料的下层的衬底的方法。 该方法包括以下步骤：顶层的非晶化，以在位于暴露表面和非晶化界面之间的顶层中形成非晶区域，该界面下面的顶层部分被遮蔽以及非晶化，并保留为 晶体结构; 重结晶非晶区域同时也在界面处产生缺陷网络，其中网络形成与顶层的晶体结构的位错的边界，并且包含位于界面下方的顶层部分中的位错。 另外，通过该方法得到的基板。

公开(公告)号：US07645486B2

公开(公告)日：2010-01-12

申请号：US11677696

申请日：2007-02-22

Applicant: Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven R. A. Van Aerde ,  Marinus J. M. De Blank ,  Cornelius A. Van Der Jeugd

Inventor： Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven R. A. Van Aerde ,  Marinus J. M. De Blank ,  Cornelius A. Van Der Jeugd

IPC: C23C16/40

CPC classification number: H01L21/31612 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271

Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapor deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.

Abstract translation: 本发明涉及一种制造低粗糙度的二氧化硅层的方法，其包括通过低压化学气相沉积（LPCVD）工艺在衬底上沉积二氧化硅层，该沉积工艺同时采用原硅酸四乙酯（TEOS ）作为膜沉积的源材料和与TEOS不反应的稀释气体流，使得稀释气体/ TEOS流量比在0.5和100之间; 并在600℃和1200℃之间的温度下将二氧化硅层退火10分钟至6小时。

公开(公告)号：US20090014720A1

公开(公告)日：2009-01-15

申请号：US12165365

申请日：2008-06-30

Applicant: Carlos MAZURE ,  Ian Cayrefourcq ,  Konstantin Bourdelle

Inventor： Carlos MAZURE ,  Ian Cayrefourcq ,  Konstantin Bourdelle

IPC: H01L21/30 ,  H01L29/04

CPC classification number: H01L21/187 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/045

Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.

Abstract translation: 本发明涉及一种处理由半导体材料制成的结构的方法，其中该结构包括限定具有缺陷的公共接口的第一和第二基板。 所述方法包括形成称为所述无组织层的层，所述层包括所述界面，其中所述晶格的至少一部分被混杂; 并重新组织无组织层的晶格，以迫使缺陷更深地进入第一衬底。

公开(公告)号：US20080303061A1

公开(公告)日：2008-12-11

申请号：US11910104

申请日：2006-03-29

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/265 ,  H01L21/762 ,  H01L29/161

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694

Abstract: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method.

Abstract translation: 一种用于制造具有第一材料的顶层和其晶格参数不同于第一材料的第二材料的下层的衬底的方法。 该方法包括以下步骤：顶层的非晶化，以在位于暴露表面和非晶化界面之间的顶层中形成非晶区域，该界面下面的顶层部分被遮蔽以及非晶化，并保留为 晶体结构; 重结晶非晶区域同时也在界面处产生缺陷网络，其中网络形成与顶层的晶体结构的位错的边界，并且包含位于界面下方的顶层部分中的位错。 另外，通过该方法得到的基板。

公开(公告)号：US07407548B2

公开(公告)日：2008-08-05

申请号：US10916254

申请日：2004-08-11

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

IPC: C30B25/04

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。

公开(公告)号：US20080102601A1

公开(公告)日：2008-05-01

申请号：US11877456

申请日：2007-10-23

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/30

CPC classification number: H01L21/02667 ,  H01L21/2022 ,  H01L21/76254

Abstract: This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer of material to form the thin layer comprises forming an amorphous layer in a part of the thin layer, and then recrystallizing the amorphous layer.

Abstract translation: 本发明涉及一种通过将材料层从供体衬底转移到支撑衬底，然后通过移除材料层的一部分以形成薄层来制造衬底的方法。 除去材料层的一部分以形成薄层的步骤包括在薄层的一部分中形成非晶层，然后使非晶层重结晶。

公开(公告)号：US20070281445A1

公开(公告)日：2007-12-06

申请号：US10577175

申请日：2004-10-28

Applicant: Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurelie Tauzin ,  Franck Fournel

Inventor： Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurelie Tauzin ,  Franck Fournel

IPC: H01L21/304

CPC classification number: H01L21/76254

Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.

Abstract translation: 一种用于自支撑转移细层的方法，其中将至少一种离子注入相对于源 - 衬底表面的指定深度的源极 - 衬底中。 施加加强件以与源 - 基板紧密接触，并且源 - 基板在特定时间段内在特定温度下进行热处理，以便在基本上在指定深度处产生脆弱的掩埋区域而不产生薄层， 相对于源极 - 基板的其余部分，在表面和脆化的掩埋层之间限定为热分离。 将受控的局部能量脉冲施加到源 - 衬底，以引起薄层的自支撑分离。

公开(公告)号：US20070134887A1

公开(公告)日：2007-06-14

申请号：US11677696

申请日：2007-02-22

Applicant: Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven Van Aerde ,  Marinus De Blank ,  Cornelius Van Der Jeugd

Inventor： Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven Van Aerde ,  Marinus De Blank ,  Cornelius Van Der Jeugd

IPC: H01L21/473

CPC classification number: H01L21/31612 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271

Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapour deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.

Abstract translation: 本发明涉及一种制造低粗糙度的二氧化硅层的方法，其包括通过低压化学气相沉积（LPCVD）工艺在衬底上沉积二氧化硅层，该沉积工艺同时采用原硅酸四乙酯（TEOS ）作为膜沉积的源材料和与TEOS不反应的稀释气体流，使得稀释气体/ TEOS流量比在0.5和100之间; 并在600℃和1200℃之间的温度下将二氧化硅层退火10分钟至6小时。

公开(公告)号：US20070000435A1

公开(公告)日：2007-01-04

申请号：US11518366

申请日：2006-09-08

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。