公开(公告)号：US20080003759A1

公开(公告)日：2008-01-03

申请号：US11427457

申请日：2006-06-29

Applicant: Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US20070057343A1

公开(公告)日：2007-03-15

申请号：US11162471

申请日：2005-09-12

Applicant: Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

Inventor： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L28/40

Abstract: A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

Abstract translation: 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：US20070026659A1

公开(公告)日：2007-02-01

申请号：US11161217

申请日：2005-07-27

Applicant: Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

Inventor： Anil Chinthakindi ,  Douglas Coolbaugh ,  John Florkey ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Anthony Stamper ,  Kunal Vaed

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/20

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Abstract translation: 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US06992344B2

公开(公告)日：2006-01-31

申请号：US10319724

申请日：2002-12-13

Applicant: Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed ,  Richard P. Volant

Inventor： Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Kenneth J. Stein ,  Kunal Vaed ,  Richard P. Volant

IPC: H01L27/108

CPC classification number: H01L28/90 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02258 ,  H01L21/0228 ,  H01L21/31604 ,  H01L21/76807 ,  H01L21/76831 ,  H01L28/40 ,  H01L28/86

Abstract: The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

Abstract translation: 本发明涉及具有高k电介质层的独特的高表面积BEOL电容器结构及其制造方法。 这些高表面积BEOL电容器结构可用于模拟和混合信号应用。 电容器形成在具有沟槽内的基座的沟槽内，以提供额外的表面积。 顶部和底部电极使用大马士革集成方案创建。 电介质层被形成为多层电介质膜，该多层电介质膜包括例如Al 2 O 3 O 3，Al 2 O 3 O 3， / Ta 2 O 5，O 2 O 3 / Ta 2 O 2， 2/3/3/3等等。 电介质层可以通过诸如原子层沉积或化学气相沉积的方法沉积。 电容器中使用的电介质层也可以通过金属前体的阳极氧化产生高介电常数氧化物层。

公开(公告)号：US20050245063A1

公开(公告)日：2005-11-03

申请号：US10709357

申请日：2004-04-29

Applicant: Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

Inventor： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01P11/00

CPC classification number: H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract translation: 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20120133022A1

公开(公告)日：2012-05-31

申请号：US13359634

申请日：2012-01-27

Applicant: Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L29/92 ,  H01L29/8605

CPC classification number: H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract translation: 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US07763954B2

公开(公告)日：2010-07-27

申请号：US12170489

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

Abstract translation: 半导体结构。 半导体结构包括：在衬底内具有至少一个金属布线层的衬底; 在所述基板的表面上的绝缘层; 绝缘层内的电感器; 和绝缘层内的引线接合焊盘。 电感器和引线接合焊盘基本上是共面的。 电感器的高度大于引线接合焊盘的高度。

公开(公告)号：US07732295B2

公开(公告)日：2010-06-08

申请号：US12170473

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L21/20

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract translation: 一种形成半导体衬底的方法。 提供基板。 衬底内至少有一个金属布线层。 第一绝缘层沉积在衬底的表面上。 引线接合焊盘的一部分形成在第一绝缘层内。 第二绝缘层沉积在第一绝缘层上。 电感器使用图案化板工艺在第二绝缘层内。 所述引线接合焊盘的剩余部分形成在所述第二绝缘层内，其中所述引线接合焊盘的至少一部分与所述电感器基本上共面。

公开(公告)号：US07573117B2

公开(公告)日：2009-08-11

申请号：US12174047

申请日：2008-07-16

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

Abstract translation: 半导体结构。 半导体结构包括：在衬底内具有金属布线层的衬底; 衬底上方的覆盖层; 覆盖层上方的绝缘层; 绝缘层上方的第一层可光成像材料; 第一层可光成像材料上方的氧化层; 位于氧化层上方的第二层可光成像材料; 电感; 和引线键合垫。 电感器的第一部分在第二层可光成像材料中，氧化层，第一层可光成像材料，绝缘层和封盖层。 电感器的第二部分仅在第二层可光成像材料中。 导线焊盘仅在第一层可光成像材料，绝缘层和封盖层中。

公开(公告)号：US20080290458A1

公开(公告)日：2008-11-27

申请号：US12170489

申请日：2008-07-10

Applicant: Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

Inventor： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  John Edward Florkey ,  Jeffrey Peter Gambino ,  Zhong-Xiang He ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC: H01L29/00

CPC classification number: H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

Abstract translation: 半导体结构。 半导体结构包括：在衬底内具有至少一个金属布线层的衬底; 在所述基板的表面上的绝缘层; 绝缘层内的电感器; 和绝缘层内的引线接合焊盘。 电感器和引线接合焊盘基本上是共面的。 电感器的高度大于引线接合焊盘的高度。