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    System and method for erasing a memory cell
    31.
    发明授权
    System and method for erasing a memory cell 有权
    擦除存储单元的系统和方法

    公开(公告)号：US07167398B1

    公开(公告)日：2007-01-23

    申请号：US11062641

    申请日：2005-02-23

    Applicant: Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

    Inventor： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

    IPC: G11C11/34 ,  G11C16/04

    CPC classification number: G11C16/0475 ,  G11C16/14 ,  H01L29/66833 ,  H01L29/7923

    Abstract: A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

    Abstract translation: 一种方法擦除包括一组存储单元的半导体器件的存储单元。 每个存储单元包括一组存储区域。 该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

    ESD implant following spacer deposition
    35.
    发明授权
    ESD implant following spacer deposition 有权
    间隔物沉积后的ESD植入

    公开(公告)号：US06900085B2

    公开(公告)日：2005-05-31

    申请号：US09891885

    申请日：2001-06-26

    Applicant: Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

    Inventor： Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

    IPC: H01L27/02 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

    Abstract translation: 本发明的一个方面提供了一种用于形成具有ESD保护晶体管的IC器件的方法。 根据本发明的一个方面，ESD保护晶体管具有轻掺杂，然后在形成间隔物之后，进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管。 间隔物可以与其他晶体管的间隔物同时形成，例如器件的外围区域中的其它晶体管。

    Planar transistor structure using isolation implants for improved Vss resistance and for process simplification
    36.
    发明授权
    Planar transistor structure using isolation implants for improved Vss resistance and for process simplification 有权
    使用隔离植入物的平面晶体管结构，用于改善Vss电阻和工艺简化

    公开(公告)号：US06740926B1

    公开(公告)日：2004-05-25

    申请号：US10032646

    申请日：2001-12-27

    Applicant: Mark Randolph

    Inventor： Mark Randolph

    IPC: H01L29788

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11531 ,  H01L29/0692 ,  H01L29/7881

    Abstract: A planar transistor structure is disclosed that minimizes resistance in the source region and simplifies fabrication of the semiconductor device. The device includes a row of transistors where each transistor includes a stack gate structure and a drain, and a layer of type-2 polysilicon is used to interconnect the transistors in each row. A source region is provided adjacent to the layer of type-2 polysilicon that includes a contact and a N-type junction extending across the source region that provides a planar electrical path between the drains of the transistors and the contact, thereby reducing resistance of the source region.

    Abstract translation: 公开了平面晶体管结构，其最小化源极区域中的电阻并且简化了半导体器件的制造。 该器件包括一排晶体管，其中每个晶体管包括堆叠栅极结构和漏极，并且使用2层多晶硅层来互连每行中的晶体管。 源极区域被设置为与包括接触的类型2多晶硅层相邻，并且跨越源极区延伸的N型结，其提供在晶体管的漏极和触点之间的平面电路径，由此降低 源区。

    Method and system for gate stack reoxidation control
    38.
    发明授权
    Method and system for gate stack reoxidation control 失效
    栅堆叠再氧化控制方法与系统

    公开(公告)号：US6015736A

    公开(公告)日：2000-01-18

    申请号：US993787

    申请日：1997-12-19

    Applicant: Scott D. Luning ,  Mark Randolph

    Inventor： Scott D. Luning ,  Mark Randolph

    IPC: H01L21/28 ,  H01L21/26

    CPC classification number: H01L21/28273 ,  Y10S438/911 ,  Y10T29/41

    Abstract: A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.

    Abstract translation: 公开了一种在半导体上提供至少一个存储单元的系统和方法。 所述方法和系统包括在半导体上提供隧道势垒，提供至少一个具有拐角的浮动栅极，以及氧化隧道势垒，半导体的一部分和至少一个浮动栅极。 包括拐角的至少一个浮动栅极的一部分设置在隧道势垒上方。 半导体的部分以第一速率氧化，并且至少一个浮栅的至少角部以第二速率氧化。 第二速率足够高于第一速率，以便为至少一个浮动门的拐角的特定四舍五入提供距离至少一个浮动栅极的角的距离的隧道势垒的期望厚度。

    Method and system for selected source during read and programming of flash memory
    39.
    发明授权
    Method and system for selected source during read and programming of flash memory 失效
    闪存读取和编程期间所选源的方法和系统

    公开(公告)号：US5949718A

    公开(公告)日：1999-09-07

    申请号：US992622

    申请日：1997-12-17

    Applicant: Mark Randolph ,  Collin Bill ,  Michael Van Buskirk

    Inventor： Mark Randolph ,  Collin Bill ,  Michael Van Buskirk

    IPC: G11C16/04 ,  G11C16/00

    CPC classification number: G11C16/0416

    Abstract: A system and method for providing a flash memory is disclosed. The flash memory includes a plurality of memory cells. Each memory cell includes a source and a gate. The method and system include providing a plurality of word lines and a plurality of select devices. Each word line is coupled with the gate of each memory cell of a portion of the plurality of memory cells. Each word line provides a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells. The plurality of select devices correspond with the plurality of word lines. Each select device is coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line. Each select device couples the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell. The method and system reduce the number of memory cells coupled in parallel with the memory cell during the read.

    Abstract translation: 公开了一种用于提供闪速存储器的系统和方法。 闪存包括多个存储单元。 每个存储单元包括源和门。 该方法和系统包括提供多个字线和多个选择装置。 每个字线与多个存储器单元的一部分的每个存储单元的栅极耦合。 每个字线在多个存储器单元的该部分的存储单元的读取期间向多个存储器单元的一部分提供特定的电压。 多个选择装置对应于多个字线。 每个选择装置与多个存储单元的与对应字线耦合的部分的每个存储单元的源耦合。 每个选择装置在存储器单元的读取期间将多个存储单元的该部分的每个存储器单元的源与特定电位耦合。 该方法和系统在读取期间减少与存储器单元并联耦合的存储器单元的数量。

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