公开(公告)号：USRE36875E

公开(公告)日：2000-09-19

申请号：US572516

申请日：1995-12-14

申请人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

发明人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4072 ,  G11C11/46 ,  G11C29/46

摘要： Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

摘要翻译： 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少一次外部+ E计数，复位后施加RAS + EE信号，并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。

公开(公告)号：US5629895A

公开(公告)日：1997-05-13

申请号：US639997

申请日：1996-04-30

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5583813A

公开(公告)日：1996-12-10

申请号：US461916

申请日：1995-06-05

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5544121A

公开(公告)日：1996-08-06

申请号：US463565

申请日：1995-06-05

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US4984210A

公开(公告)日：1991-01-08

申请号：US565400

申请日：1990-08-10

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

IPC分类号： G11C11/407 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

公开(公告)号：US4954992A

公开(公告)日：1990-09-04

申请号：US269757

申请日：1988-11-08

申请人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

发明人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G11C7/1057 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/062 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

摘要翻译： 一种动态随机存取存储器件包括一对写入数据传送总线，用于传送要被写入的数据，一对读出数据传输总线，用于传送要被读取的数据，附加地和独立于写入数据传输总线 对和由CMOS晶体管形成的多个电流镜型读出放大器，并且每个放大器设置在位线对和读出数据传输总线对之间，并且具有连接到相应位线对和读出数据的输入节点 传输总线对形成其输出节点。 响应于比传统的触发器型读出放大器被激活的时间早的列解码器的输出，CMOS晶体管的电流镜式读出放大器被激活。

公开(公告)号：US4943960A

公开(公告)日：1990-07-24

申请号：US337976

申请日：1989-04-14

申请人： Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/406 ,  G11C11/4074

摘要： There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line pair. During the self-controlled refresh cycle, the bit line pair is equalized and precharged to a voltage lower than Vcc/2. When it is attempted to set the time interval between the self-refresh cycles in order to reduce current consumption, the level of voltage stored in the memory cell capacitor tends to decrease due to charge leakage. However, it is implemented to provide and keep a potential difference between the precharge voltage on the bit line pair and the voltage stored in the capacitor thereby to secure the desired sensing margin for the sense amplifier.

摘要翻译： 公开了一种能够进行周期性自刷新操作周期的动态随机存取存储器件。 DRAM包括用于检测自刷新模式的指定的检测器电路和用于产生用于对位线对预充电的电压的电压发生器电路。 在自控刷新周期期间，位线对被均衡并预充电到低于Vcc / 2的电压。 当为了减少电流消耗而尝试设置自刷新周期之间的时间间隔时，由于电荷泄漏，存储在存储单元电容器中的电压电平趋于降低。 然而，实现了提供并保持位线对上的预充电电压和存储在电容器中的电压之间的电位差，从而确保感测放大器所需的感测余量。

公开(公告)号：US4903238A

公开(公告)日：1990-02-20

申请号：US201787

申请日：1988-06-02

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Katsumi Dosaka

IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C11/409 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C5/14

摘要： A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.

摘要翻译： 诸如静态RAM（随机存取存储器）装置的半导体存储器件包括连接在两个I / O线和地之间的n沟道场效应晶体管的接地连接电路。 用于预充电的预充电电路和接地连接电路都响应于与外部施加的外部芯片选择信号同步的信号而工作。 因此，可以防止在外部芯片选择信号改变之前产生的电源电压的波动导致的访问延迟。

公开(公告)号：US4837747A

公开(公告)日：1989-06-06

申请号：US126349

申请日：1987-11-30

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

IPC分类号： G11C8/12 ,  G11C29/00

CPC分类号： G11C29/806 ,  G11C8/12

摘要： A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

摘要翻译： 存储单元阵列被分成四个块＃1到＃4。 当行地址信号RA8等于“0”时，块＃1和＃3被操作。 当行地址信号RA8等于“1”时，块＃2和＃4被操作。 在每个块中提供备用行子解码器。 块＃1和＃2中的备用行子解码器通过单个备用解码器选择线连接到备用主主解码器。 块＃2和＃4中的备用行子解码器通过另一个备用解码器选择线连接到另一备用行主解码器。 备用主解码器响应于行地址信号RA8和行地址信号RA2，RA2。 。 。 ，RA7，RA7，用于在处于操作状态的块中操作备用行子解码器。

公开(公告)号：US4809230A

公开(公告)日：1989-02-28

申请号：US938065

申请日：1986-12-04

申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/4076 ,  G11C11/4094

摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

摘要翻译： MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。