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    Three-dimensional semiconductor memory devices and methods of forming the same
    32.
    发明授权
    Three-dimensional semiconductor memory devices and methods of forming the same 有权
    三维半导体存储器件及其形成方法

    公开(公告)号：US09356033B2

    公开(公告)日：2016-05-31

    申请号：US14810845

    申请日：2015-07-28

    Applicant: Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    Inventor： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L27/115

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

    Abstract: Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

    Abstract translation: 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

    Semiconductor memory device and method of fabricating the same
    34.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09224753B2

    公开(公告)日：2015-12-29

    申请号：US14599933

    申请日：2015-01-19

    Applicant: Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    Inventor： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/49

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

    Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

    Abstract translation: 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透绝缘图案的垂直沟道结构和彼此交替重复堆叠的栅电极。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以被延伸以连续地覆盖第二栅极导电层的表面。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    35.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20150243675A1

    公开(公告)日：2015-08-27

    申请号：US14599933

    申请日：2015-01-19

    Applicant: Tai-Soo LIM ,  Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Myoungbum LEE ,  Yong-Chae JUNG

    Inventor： Tai-Soo LIM ,  Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Myoungbum LEE ,  Yong-Chae JUNG

    IPC: H01L27/115 ,  H01L29/49

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

    Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

    Abstract translation: 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透彼此交替且重复堆叠的绝缘图案和栅电极的垂直沟道结构。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以延伸以连续地覆盖第二栅极导电层的表面。

    Semiconductor memory device and method of forming the same
    38.
    发明授权
    Semiconductor memory device and method of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08415742B2

    公开(公告)日：2013-04-09

    申请号：US13442804

    申请日：2012-04-09

    Applicant: Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L27/12 ,  H01L21/4763

    CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

    Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

    Abstract translation: 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

    Nonvolatile memory device having a fixed charge layer
    39.
    发明授权
    Nonvolatile memory device having a fixed charge layer 有权
    具有固定电荷层的非易失性存储器件

    公开(公告)号：US08283719B2

    公开(公告)日：2012-10-09

    申请号：US12894615

    申请日：2010-09-30

    Applicant: ZongLiang Huo ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungmok Shin ,  Sunjung Kim

    Inventor： ZongLiang Huo ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungmok Shin ,  Sunjung Kim

    IPC: H01L29/792 ,  H01L29/788 ,  H01L29/76

    CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

    Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

    Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 层叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

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