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    Vector completion mask handling
    32.
    发明授权
    Vector completion mask handling 有权
    矢量完成掩码处理

    公开(公告)号：US08510536B2

    公开(公告)日：2013-08-13

    申请号：US13535685

    申请日：2012-06-28

    Applicant: Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

    Inventor： Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

    IPC: G06F15/00 ,  G06F15/76

    CPC classification number: G06F9/3824 ,  G06F9/30036 ,  G06F15/8084

    Abstract: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

    Abstract translation: 提供矢量完成掩码（VCM）处理技术。 数据结构包括用于特定操作的每个操作数的掩码字段。 处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。 如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。 如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

    Vector Completion Mask Handling
    33.
    发明申请
    Vector Completion Mask Handling 有权
    矢量完成面具处理

    公开(公告)号：US20120272046A1

    公开(公告)日：2012-10-25

    申请号：US13535685

    申请日：2012-06-28

    Applicant: Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

    Inventor： Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

    IPC: G06F9/302

    CPC classification number: G06F9/3824 ,  G06F9/30036 ,  G06F15/8084

    Abstract: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

    Abstract translation: 提供矢量完成掩码（VCM）处理技术。 数据结构包括用于特定操作的每个操作数的掩码字段。 处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。 如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。 如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

    Method And Apparatus For Virtualized Microcode Sequencing
    36.
    发明申请
    Method And Apparatus For Virtualized Microcode Sequencing 审中-公开
    用于虚拟化微代码排序的方法和装置

    公开(公告)号：US20110296096A1

    公开(公告)日：2011-12-01

    申请号：US12912169

    申请日：2010-10-26

    Applicant: Xiang Zou ,  Per Hammarlund ,  Ronak Singhal ,  Hong Wang

    Inventor： Xiang Zou ,  Per Hammarlund ,  Ronak Singhal ,  Hong Wang

    IPC: G06F12/06 ,  G06F12/08

    CPC classification number: G06F9/30174 ,  G06F9/3802 ,  G06F9/3891

    Abstract: In one embodiment, the present invention includes a processor having multiple cores and an uncore. The uncore may include a microcode read only memory to store microcode to be executed in the cores (that themselves do not include such memory). The cores can include a microcode sequencer to sequence a plurality of micro-instructions (uops) of microcode that corresponds to a macro-instruction to be executed in an execution unit of the corresponding core. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有多个核心和非核心的处理器。 无孔可以包括微代码只读存储器，以存储要在核心中执行的微代码（其本身不包括这样的存储器）。 核心可以包括微代码定序器，以对应于在相应核心的执行单元中执行的宏指令的微代码的多个微指令（uop）。 描述和要求保护其他实施例。

    Method and apparatus for efficient resource utilization for prescient instruction prefetch
    38.
    发明授权
    Method and apparatus for efficient resource utilization for prescient instruction prefetch 有权
    有效资源利用的方法和装置，用于预先的指令预取

    公开(公告)号：US07818547B2

    公开(公告)日：2010-10-19

    申请号：US12106184

    申请日：2008-04-18

    Applicant: Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

    Inventor： Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

    IPC: G06F9/38

    CPC classification number: G06F9/3842 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859

    Abstract: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

    Abstract translation: 装置，系统和方法的实施例通过一个或多个推测性线程增强在指令预取期间处理器资源利用的效率。 利用重命名逻辑和映射表来对推测性线程指令流中的指令进行滤波。 映射表包括一个肯定事件位，用于指示相关联的物理寄存器的内容是否反映由主线程计算的值。 线程进度信标表用于跟踪主线程和推测式辅助线程的相对进度。 基于线程进度信标表中的信息，主线程可能会影响不太可能为主线程提供性能优势的辅助线程的终止。

    Synchronizing recency information in an inclusive cache hierarchy
    39.
    发明授权
    Synchronizing recency information in an inclusive cache hierarchy 失效
    在包含缓存层次结构中同步新近度信息

    公开(公告)号：US07757045B2

    公开(公告)日：2010-07-13

    申请号：US11374222

    申请日：2006-03-13

    Applicant: Christopher J. Shannon ,  Ronak Singhal ,  Per Hammarlund ,  Hermann Gartler ,  Glenn Hinton

    Inventor： Christopher J. Shannon ,  Ronak Singhal ,  Per Hammarlund ,  Hermann Gartler ,  Glenn Hinton

    IPC: G06F12/00

    CPC classification number: G06F12/123

    Abstract: In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于接收对存在于较低级高速缓存的较低级高速缓存行中的数据的高速缓存访​​问请求的方法，以及将关于下级高速缓存线的新近度信息发送到更高级高速缓存 。 较高级别的缓存可以与下级缓存一起包含，并且可以更新与高速缓存行相关联的年龄数据，从而减少高速缓存线的驱逐的可能性。 描述和要求保护其他实施例。

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