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2920 条记录 (耗时 0.036 秒)

    PULSE FILTER
    31.
    发明公开
    PULSE FILTER 审中-公开

    公开(公告)号：US20240080016A1

    公开(公告)日：2024-03-07

    申请号：US18236857

    申请日：2023-08-22

    申请人： Rambus Inc.

    发明人： Cosmin IORGA ,  Ruibing ZHANG

    IPC分类号： H03H11/04

    CPC分类号： H03H11/04

    摘要： A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.

    BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
    32.
    发明公开
    BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY 审中-公开

    公开(公告)号：US20240079079A1

    公开(公告)日：2024-03-07

    申请号：US18233257

    申请日：2023-08-11

    申请人： Rambus Inc.

    发明人： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

    IPC分类号： G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/52

    CPC分类号： G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

    摘要： A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

    Dedicated cache-related block transfer in a memory system
    33.
    发明授权
    Dedicated cache-related block transfer in a memory system 有权

    公开(公告)号：US11921650B2

    公开(公告)日：2024-03-05

    申请号：US18117119

    申请日：2023-03-03

    申请人： Rambus Inc.

    发明人： Liji Gopalakrishnan

    IPC分类号： G06F13/16 ,  G11C11/4093 ,  G11C11/4096

    CPC分类号： G06F13/1668 ,  G11C11/4093 ,  G11C11/4096

    摘要： A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

    Memory system with activate-leveling method
    38.
    发明授权
    Memory system with activate-leveling method 有权

    公开(公告)号：US11899571B2

    公开(公告)日：2024-02-13

    申请号：US17673277

    申请日：2022-02-16

    申请人： Rambus Inc.

    发明人： Frederick A. Ware ,  Craig E. Hampel

    IPC分类号： G06F12/02

    CPC分类号： G06F12/02 ,  G06F12/0292

    摘要： Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    39.
    发明公开
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 审中-公开

    公开(公告)号：US20240036975A1

    公开(公告)日：2024-02-01

    申请号：US18230403

    申请日：2023-08-04

    申请人： Rambus Inc.

    发明人： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1076 ,  G06F11/1048

    摘要： A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.