公开(公告)号：US06949472B1

公开(公告)日：2005-09-27

申请号：US10838720

申请日：2004-05-03

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/306 ,  H01L21/31 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/02046 ,  H01L21/76862 ,  H01L21/76865

Abstract: A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.

Abstract translation: 一种用于在单个镶嵌，双镶嵌或其他接触开口结构上沉积阻挡层的新方法。 该方法消除了对结构的氩离子轰击的预清洁的需要，从而减少或消除了下面的导电层的表面的损伤和铜颗粒溅射到通孔或其他接触开口侧壁。 该方法包括在基底上制造单个镶嵌，双镶嵌或其它接触开口结构; 可以任选地预先使用氮或氢等离子体对结构进行预清洗; 在结构的侧壁和底部上沉积薄金属阻挡层; 并且在结构的底部和侧壁上重新分布或重新溅射阻挡层。

公开(公告)号：US20050170648A1

公开(公告)日：2005-08-04

申请号：US11056758

申请日：2005-02-11

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

公开(公告)号：US06815336B1

公开(公告)日：2004-11-09

申请号：US09160965

申请日：1998-09-25

Applicant: Shau-Lin Shue ,  Syun-Ming Jang

Inventor： Shau-Lin Shue ,  Syun-Ming Jang

IPC: H01L214763

CPC classification number: H01L21/2885 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684

Abstract: Methods are disclosed to improve the planarization of copper damascene by the steps of patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or by dry or wet chemical etching, stripping the photo resist, and a subsequent chemical mechanical planarization of the copper damascene. Lastly a cap layer is applied to the planarized surface. In a variant of the disclosed method a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use. These steps provide benefits such as improved uniformity of the wafer surface, reduce the dishing of metal lines (trenches) and pads, and reduce oxide erosion.

Abstract translation: 公开了通过以下步骤来改善铜镶嵌的平面化的步骤：使用反色调光掩模或金属线的反色调光掩模在铜镶嵌光致抗蚀剂上进行图案化，通过反向电镀或通过干或湿去除多余的铜 化学蚀刻，剥离光致抗蚀剂，以及铜镶嵌件的随后的化学机械平面化。 最后，将覆盖层施加到平坦化表面。 在所公开的方法的变型中，使用金属线的更宽松的反向色调光掩模，这对于实际使用可能是更理想的。 这些步骤提供了诸如改善晶片表面的均匀性，减少金属线（沟槽）和焊盘的凹陷以及减少氧化物侵蚀的益处。

公开(公告)号：US06797144B2

公开(公告)日：2004-09-28

申请号：US10141277

申请日：2002-05-08

Applicant: Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: C25D712

CPC classification number: H01L21/2885 ,  C25D7/123 ,  H01L21/76877

Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

Abstract translation: 一种用于在电镀工艺之后原位清洁电沉积表面的方法，包括提供第一电极组件和第二电极组件; 在第一电极组件和第二电极组件上施加第一电流密度以执行电沉积过程; 执行电沉积工艺以将金属电沉积到第二电极组件的电沉积表面上; 并且相对于第一电流密度，第二电流密度具有相对于第一极性反转的第二电流密度跨越第一电极组件和第二电极组件，第二电流密度具有相对较低的电流密度。

公开(公告)号：US06737352B2

公开(公告)日：2004-05-18

申请号：US10194630

申请日：2002-07-12

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Ya

IPC: H01L214763

CPC classification number: H01L21/76802

Abstract: A method to prevent particle generation from sputtering clean is disclosed, the method comprises of forming a dielectric layer on a substrate, forming a nitrogen-containing dielectric layer on the dielectric layer, forming a plurality of contact holes in the dielectric layer and the nitrogen-containing dielectric layer, coating a sacrificial layer into the contact holes and on the nitrogen-containing dielectric layer, removing the sacrificial layer and the nitrogen-containing dielectric layer on top of the dielectric layer, removing said sacrificial layer in said contact holes and performing an argon sputtering clean.

Abstract translation: 公开了一种防止溅射清洁产生颗粒的方法，该方法包括在基板上形成电介质层，在电介质层上形成含氮介电层，在电介质层中形成多个接触孔， 在所述接触孔和所述含氮电介质层上涂覆牺牲层，在所述电介质层的顶部上去除所述牺牲层和所述含氮介电层，去除所述接触孔中的所述牺牲层，并执行 氩气溅射清洗。

公开(公告)号：US06551915B2

公开(公告)日：2003-04-22

申请号：US09898980

申请日：2001-07-03

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L2144

CPC classification number: H01L21/76828 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76826

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

公开(公告)号：US06436825B1

公开(公告)日：2002-08-20

申请号：US09541481

申请日：2000-04-03

Applicant: Shau-Lin Shue

Inventor： Shau-Lin Shue

IPC: H01L2144

CPC classification number: H01L21/76856 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76864

Abstract: A process in the fabrication of integrated circuits has been developed for copper diffusion barrier layer. This invention teaches a method of barrier formation by the deposition by physical vapor deposition (PVD) sputtering (reactive sputtering for nitride compounds) or chemical vapor deposition (CVD) of a copper metal diffusion barrier layer, which consists of the following materials: TaN, Ta, TiN, or WN. Next in the process, is the plasma silation and silicon doping of the barrier layer material followed by high temperature thermal annealing. Scanning electron microscope (SEM) analysis of the silated barrier materials show amorphous films with clusters of silicide material with low silicon concentration and high film density (>99%). Low diffusion properties (amorphous films lack grains for fast grain boundary diffusion) and good chemical vapor deposited (CVD) copper seed layer adhesion, are found with the both TiSiN and TaSiN barrier layers made by this method. The current invention applies to lining both a single and dual damascene structure to form copper metal barrier layers and adhesive copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.

Abstract translation: 已经开发了用于铜扩散阻挡层的集成电路制造工艺。 本发明教导了通过物理气相沉积（PVD）溅射（氮化物的反应溅射）或铜金属扩散阻挡层的化学气相沉积（CVD）沉积的阻挡层形成方法，其由以下材料组成：TaN， Ta，TiN或WN。 接下来的过程中，是阻挡层材料的等离子体硅化和硅掺杂，随后进行高温热退火。 硅酸盐屏障材料的扫描电子显微镜（SEM）分析显示出具有低硅浓度和高膜密度（> 99％）的硅化物材料簇的非晶膜。 通过该方法制备的TiSiN和TaSiN阻挡层都发现了低扩散性能（非晶膜缺乏快速晶界扩散的晶粒）和良好的化学气相沉积（CVD）铜种子层粘附性。 本发明适用于在铜的电化学沉积（ECD）之前的单镶嵌和双镶嵌结构衬底上形成铜金属阻挡层和用于互连和通孔的粘合剂铜籽晶层。

公开(公告)号：US06242338B1

公开(公告)日：2001-06-05

申请号：US09422175

申请日：1999-10-22

Applicant: Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

Inventor： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

IPC: H01L214763

CPC classification number: H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/321 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888

Abstract: A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

Abstract translation: 已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。 该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。 薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

公开(公告)号：US6083835A

公开(公告)日：2000-07-04

申请号：US121707

申请日：1998-07-24

Applicant: Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76856 ,  H01L21/7684 ,  H01L21/76849

Abstract: A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this layer so that it covers only the copper in the damascene trench. Then, while the IMD is deposited, some of the chromium in the alloy gets selectively oxidized, resulting in a self-aligned barrier layer of chromium oxide at the copper to IMD interface.

Abstract translation: 描述了在集成电路内形成镶嵌线的工艺。 在沟槽被填充和平坦化之后，存在铜的正常凹陷。 然后通过在大马士革布线上沉积一层铬铜合金，然后平坦化该层，使其仅覆盖大马士革沟槽中的铜而消除。 然后，当沉积IMD时，合金中的一些铬被选择性地氧化，导致在铜到IMD界面处的氧化铬的自对准势垒层。

公开(公告)号：US08941239B2

公开(公告)日：2015-01-27

申请号：US13586676

申请日：2012-08-15

Applicant: Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

Inventor： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

IPC: H01L23/48 ,  H01L21/14

CPC classification number: H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

Abstract: A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

Abstract translation: 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。