公开(公告)号：US20240241785A1

公开(公告)日：2024-07-18

申请号：US18213907

申请日：2023-06-26

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: G06F11/10 ,  G06F11/30 ,  G06F13/16 ,  H04L1/20

CPC classification number: G06F11/1068 ,  G06F11/3037 ,  G06F13/1673 ,  H04L1/205

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results and includes a compensation control mechanism selection circuit which selects a corresponding compensation control mechanism according to the monitored results and set it as a currently-operating compensation control mechanism to control the hardware circuits to operate in compliance with the currently-operating compensation control mechanism.

公开(公告)号：US20240241647A1

公开(公告)日：2024-07-18

申请号：US18215183

申请日：2023-06-28

Applicant: Silicon Motion, Inc.

Inventor： Fu-Jen Shih

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G11C7/1048 ,  G11C2207/2254

Abstract: An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

公开(公告)号：US20240233849A1

公开(公告)日：2024-07-11

申请号：US18094989

申请日：2023-01-10

Applicant: Silicon Motion, Inc.

Inventor： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC: G11C29/12

CPC classification number: G11C29/12005 ,  G11C29/1201

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends an error injection access command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the error injection access command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with controlling a memory cell array of flash memory device generating failure errors.

公开(公告)号：US20240201902A1

公开(公告)日：2024-06-20

申请号：US18383239

申请日：2023-10-24

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting CHIU

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0679

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; reading user data of the first logical address range from a first address of the RAM and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into the flash module.

公开(公告)号：US12014063B2

公开(公告)日：2024-06-18

申请号：US18098129

申请日：2023-01-18

Applicant: Silicon Motion, Inc.

Inventor： Ching-Hui Lin

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0605 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

公开(公告)号：US20240184485A1

公开(公告)日：2024-06-06

申请号：US18236398

申请日：2023-08-21

Applicant: Silicon Motion, Inc.

Inventor： Ming-Yu Tsai

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, and the command processing circuit is arranged to: receive a command from the host device; utilize multiple check items to check the command to generate at least one check result; and convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.

公开(公告)号：US20240170036A1

公开(公告)日：2024-05-23

申请号：US18389227

申请日：2023-11-14

Applicant: Silicon Motion, Inc.

Inventor： Jieh-Hsin Chien ,  Yi-Hua Pao

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/4074

Abstract: A data protection method applied to a data storage device including a volatile memory and a non-volatile flash memory is provided. The data protection method includes, executing a protection program after the data storage device is coupled to a host, to perform following steps: shielding a refresh command from the host; monitoring a working voltage of the data storage device through a voltage sensing module; determining whether the working voltage is lower than a threshold; when it is determined that the working voltage is lower than the threshold, providing the data storage device with power to trigger the refresh command to write the data in the volatile memory into the non-volatile flash memory. Therefore, the writing times of the data storage device are reduced, the performance degradation of the data storage device is avoided, and the service life of the data storage device is extended.

公开(公告)号：US20240154624A1

公开(公告)日：2024-05-09

申请号：US18413007

申请日：2024-01-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/09 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  H03M13/00 ,  H03M13/15

CPC classification number: H03M13/098 ,  G06F11/1072 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/10 ,  H03M13/1515 ,  H03M13/611 ,  G11C16/26

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US11977767B2

公开(公告)日：2024-05-07

申请号：US17693431

申请日：2022-03-14

Applicant: Silicon Motion, Inc.

Inventor： Yi-Kai Pai

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

公开(公告)号：US20240143226A1

公开(公告)日：2024-05-02

申请号：US18220293

申请日：2023-07-11

Applicant: Silicon Motion, Inc.

Inventor： Po-Lin Wu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0679

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determine a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller performs a garbage collection and updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.