公开(公告)号：US20210342682A1

公开(公告)日：2021-11-04

申请号：US17367633

申请日：2021-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STANLEY HONG ,  ANH LY ,  THUAN VU ,  HIEN PHAM ,  KHA NGUYEN ,  HAN TRAN

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US11120881B2

公开(公告)日：2021-09-14

申请号：US17075691

申请日：2020-10-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Kha Nguyen ,  Hien Pham ,  Stanley Hong ,  Stephen T. Trinh

IPC: G11C5/14 ,  G11C16/14 ,  H02M3/07 ,  G11C16/30

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

公开(公告)号：US20210090654A1

公开(公告)日：2021-03-25

申请号：US17095661

申请日：2020-11-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for providing temperature compensation in an analog memory array. A method and related system are disclosed for compensating for temperature changes in an array of memory cells by measuring an operating temperature within the array of memory cells and changing a threshold voltage of a selected memory cell in the array of memory cells to compensate for a change in the operating temperature.

公开(公告)号：US20210082516A1

公开(公告)日：2021-03-18

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/24

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

公开(公告)号：US10943661B2

公开(公告)日：2021-03-09

申请号：US16550253

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20210065817A1

公开(公告)日：2021-03-04

申请号：US16803401

申请日：2020-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  G11C16/16

Abstract: A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.

公开(公告)号：US10833178B2

公开(公告)日：2020-11-10

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20200350015A1

公开(公告)日：2020-11-05

申请号：US16930777

申请日：2020-07-16

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  STEVEN LEMKE ,  NHAN DO ,  VIPIN TIWARI ,  MARK REITEN

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

公开(公告)号：US20200349422A1

公开(公告)日：2020-11-05

申请号：US16449205

申请日：2019-06-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stephen Trinh ,  Thuan Vu ,  Stanley Hong ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G11C16/08

Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

公开(公告)号：US20200342938A1

公开(公告)日：2020-10-29

申请号：US16503355

申请日：2019-07-03

Applicant: Silicon Storage Technology, Inc.

Inventor： HIEU VAN TRAN ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  ANH LY ,  HAN TRAN ,  KHA NGUYEN ,  HIEN PHAM

IPC: G11C11/56 ,  G11C11/16 ,  G11C11/4074 ,  G06F17/16 ,  G06N3/06

Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.