公开(公告)号：US5717645A

公开(公告)日：1998-02-10

申请号：US797810

申请日：1997-02-07

Applicant: Subramani Kengeri ,  Chitranjan N. Reddy

Inventor： Subramani Kengeri ,  Chitranjan N. Reddy

IPC: G11C5/02 ,  G11C11/409 ,  G11C13/00

CPC classification number: G11C5/025 ,  G11C11/409

Abstract: A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.

Abstract translation: 公开了一种随机存取存储器（RAM）（10）。 驱动器线路（28）的网络在连接控制组24与列解码组（26a和26b）的多个核心阵列（12a-12p）​​之间延伸，并且列解码组（26a和26b）与有义组46 芯阵列（12a-12p）​​。 驱动器线路28包括用于将来自控制组24的预解码信号和时钟信号耦合到列解码组（26a和26b）的预解码线30和时钟线32。 此外，驱动器线28包括列选择线34和感测驱动器线36，用于将列选择信号和来自列解码组（26a和26b）的读出放大器使能信号耦合到感测组46.感测组46包括读出放大器 80，其被解码的传输门库（70a和70b）在阵列象限42之间共享。 预充电电路82和均衡电路86的有利位置提供了紧凑的感测组结构46。

公开(公告)号：US09196548B2

公开(公告)日：2015-11-24

申请号：US13729843

申请日：2012-12-28

Applicant: Mahbub Rashed ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211

Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

Abstract translation: 公开了使用分段沟槽自对准硅层选择性地连接翅片结构的方法，以及所得到的装置。 实施例包括：在衬底上提供至少一个栅极结构; 在与所述至少一个栅极结构相交的垂直方向上提供第一和第二鳍结构; 以及提供自对准层的第一段，所述第一段沿着水平方向形成并且与所述第二鳍结构连接并与所述第一鳍结构分离。

公开(公告)号：US20140001563A1

公开(公告)日：2014-01-02

申请号：US13539830

申请日：2012-07-02

Applicant: Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

Abstract translation: 本文公开的一个说明性器件包括限定在半导体衬底中的连续有源区，形成在连续有源区中和上方的第一和第二晶体管，第一和第二晶体管中的每一个包括形成在连续有源区中的多个掺杂区， 导电隔离电极位于第一和第二晶体管之间的连续有源区上方，导电隔离电极与导电隔离电极导电耦合。

公开(公告)号：US08547779B2

公开(公告)日：2013-10-01

申请号：US13429117

申请日：2012-03-23

Applicant: Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

Inventor： Kuoyuan Hsu ,  Ming-Chieh Huang ,  Young Suk Kim ,  Subramani Kengeri

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C7/1042 ,  G11C8/04

Abstract: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract translation: 交织存储器电路包括一个存储体，该存储体包括至少一个用于存储表示第一数据的电荷的第一存储单元，第一存储单元与第一字线和第一位线耦合。 交错存储器电路还包括与存储体耦合的本地控制电路。 交错存储器电路还包括与本地控制电路耦合的全局控制电路，包括具有用于访问第一存储器单元的第一周期和第二周期的时钟信号的交织访问，其中第二周期能够实现本地控制 触发用于访问第一存储器单元的第一读取列选择信号RSSL的第一转换。

公开(公告)号：US20130146986A1

公开(公告)日：2013-06-13

申请号：US13324740

申请日：2011-12-13

Applicant: Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L27/092 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Abstract translation: 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US20120213013A1

公开(公告)日：2012-08-23

申请号：US13461571

申请日：2012-05-01

Applicant: Subramani KENGERI ,  Chung-Cheng CHOU ,  Bharath UPPUTURI ,  Hank CHENG ,  Ming-Zhang KUO ,  Pey-Huey CHEN

Inventor： Subramani KENGERI ,  Chung-Cheng CHOU ,  Bharath UPPUTURI ,  Hank CHENG ,  Ming-Zhang KUO ,  Pey-Huey CHEN

IPC: G11C7/00 ,  G06F17/50

CPC classification number: G06F17/5045

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract translation: 存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由 （APR）和时序分析。

公开(公告)号：US20120176856A1

公开(公告)日：2012-07-12

申请号：US13429117

申请日：2012-03-23

Applicant: Kuoyuan HSU ,  Ming-Chieh HUANG ,  Young Suk KIM ,  Subramani KENGERI

Inventor： Kuoyuan HSU ,  Ming-Chieh HUANG ,  Young Suk KIM ,  Subramani KENGERI

IPC: G11C8/18 ,  G11C8/00

CPC classification number: G11C7/1042 ,  G11C8/04

Abstract: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract translation: 交织存储器电路包括一个存储体，该存储体包括至少一个用于存储表示第一数据的电荷的第一存储单元，第一存储单元与第一字线和第一位线耦合。 交错存储器电路还包括与存储体耦合的本地控制电路。 交错存储器电路还包括与本地控制电路耦合的全局控制电路，包括具有用于访问第一存储器单元的第一周期和第二周期的时钟信号的交织访问，其中第二周期能够实现本地控制 触发用于访问第一存储器单元的第一读取列选择信号RSSL的第一转换。

公开(公告)号：US20100329055A1

公开(公告)日：2010-12-30

申请号：US12824652

申请日：2010-06-28

Applicant: Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

Inventor： Kuoyuan HSU ,  Po-Hung CHEN ,  Jiann-Tseng HUANG ,  Subramani KENGERI

IPC: G11C29/00 ,  G11C17/16

CPC classification number: G11C13/00 ,  G11C5/147 ,  G11C7/00 ,  G11C7/062 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C16/26 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0045

Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

Abstract translation: 一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。

公开(公告)号：US20100254069A1

公开(公告)日：2010-10-07

申请号：US12751542

申请日：2010-03-31

Applicant: Ching-Hao SHAW ,  Subramani KENGERI

Inventor： Ching-Hao SHAW ,  Subramani KENGERI

IPC: H01G4/00 ,  H01G7/00

CPC classification number: G11C5/005 ,  G11C11/4125 ,  G11C11/417 ,  G11C29/52 ,  H01L23/5223 ,  H01L23/556 ,  H01L27/0629 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1104 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Abstract translation: 一些实施例涉及网状电容器，其提高了SER FIT速率。 在一个实施例中，电容器连接在触发器中的锁存器的输入和输出之间，使得触发器由于辐射（例如来自中子和/或α粒子）而更难翻转。 在一些实施例中，电容器直接垂直地构建在触发器的顶部，从而节省芯片布局区域。

公开(公告)号：US07733687B2

公开(公告)日：2010-06-08

申请号：US12034416

申请日：2008-02-20

Applicant: Subramani Kengeri ,  Bharath Upputuri

Inventor： Subramani Kengeri ,  Bharath Upputuri

IPC: G11C11/00

CPC classification number: G11C11/417 ,  G11C5/147 ,  G11C11/419

Abstract: A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.

Abstract translation: 存储电路包括位线; 字线 具有第一电源电压的第一电源节点; 连接到第一电源节点的第一电源线; 从由浮动节点和具有低于第一电源电压的第二电源电压的节点组成的组中选择的第二电源节点; 第二电源线，被配置为切换所述第一和第二电源节点之间的连接; 耦合第一和第二电源线的写辅助保持器（WAK）装置; 以及连接到位线，字线和第二电源线的静态随机存取存储器（SRAM）单元。