公开(公告)号：US20070045103A1

公开(公告)日：2007-03-01

申请号：US11209328

申请日：2005-08-23

申请人： Wei Lee ,  Ted Guo ,  Sang-Ho Yu

发明人： Wei Lee ,  Ted Guo ,  Sang-Ho Yu

IPC分类号： C23C14/00

CPC分类号： C23C14/185 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345

摘要： An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter reactors. The first step includes sputtering a high fraction of ionized aluminum atoms onto a relatively cold wafer, e.g., held at less than 150° C., and relatively highly biased to attract aluminum atoms into the narrow holes and etch overhangs. The second step includes more neutral sputtering onto a relatively warm wafer, e.g. held at greater than 250° C., and substantially unbiased to provide a more isotropic and uniform aluminum flux. The magnetron scanned about the back of the aluminum target may be relatively small and unbalanced in the first step and relatively large and balanced in the second.

摘要翻译： 一种铝溅射工艺，包括RF偏置晶片和两步铝填充工艺和装置，用于在两个明显不同的条件下，优选在两个不同的等离子体溅射反应器中通过溅射将铝填充到窄通孔中。 第一步包括将大部分电离铝原子溅射到相对冷的晶片上，例如保持在小于150℃，并且相当高的偏压以将铝原子吸引到窄孔中并蚀刻突出端。 第二步包括在相对温暖的晶片上的更中性的溅射，例如 保持在大于250℃，并且基本上无偏差以提供更多的各向同性和均匀的铝通量。 围绕铝靶的背面扫描的磁控管可能在第一步骤中相对较小并且不平衡，而在第二步中相对较大且平衡。

公开(公告)号：US20070022952A1

公开(公告)日：2007-02-01

申请号：US11459531

申请日：2006-07-24

申请人： Alan Ritchie ,  Wei Lee ,  Ted Guo

发明人： Alan Ritchie ,  Wei Lee ,  Ted Guo

IPC分类号： C23C14/32 ,  C23F1/00 ,  C23C16/00

CPC分类号： C23C16/45561 ,  C23C14/165 ,  C23C16/4402 ,  C23C16/4404 ,  C23C16/45565 ,  C23C16/45591 ,  Y10T29/497 ,  Y10T29/49826 ,  Y10T137/0491 ,  Y10T137/9029

摘要： Blocker plates for chemical vapor deposition chambers and methods of treating blocker plates are provided. The blocker plates define a plurality of holes therethrough and have an upper surface and a lower surface that are at least about 99.5% pure, which minimizes the nucleation of contaminating particles on the blocker plates. A physically vapor deposited coating, such as an aluminum physically vapor deposited coating, may be formed on the upper and lower surfaces of the blocker plates. Chemical vapor deposition chambers including blocker plates having a physically vapor deposited coating thereon are also provided.

摘要翻译： 提供化学气相沉积室的阻挡板和处理阻挡板的方法。 阻挡板限定穿过其中的多个孔，并且具有至少约99.5％纯度的上表面和下表面，其最大限度地减小阻挡板上的污染颗粒的成核。 可以在阻挡板的上表面和下表面上形成物理气相沉积涂层，例如铝物理气相沉积涂层。 还提供了包括其上具有物理气相沉积涂层的阻挡板的化学气相沉积室。

公开(公告)号：US06656831B1

公开(公告)日：2003-12-02

申请号：US09491563

申请日：2000-01-26

申请人： Wei Ti Lee ,  Ted Guo

发明人： Wei Ti Lee ,  Ted Guo

IPC分类号： H01L214763

CPC分类号： C23C16/34 ,  H01L21/28556

摘要： A refractory metal layer is deposited onto a substrate having high aspect ratio contracts or vias formed thereon. Next, a plasma-enhanced CVD refractory metal nitride layer is deposited on the refractory metal layer. Then, a metal layer is deposited over the metal nitride layer. The resulting metal layer is substantially void free and has reduced resistivity, and has greater effective line width. Plasma-enhanced chemical vapor deposition of the metal nitride layer comprises forming a plasma of a metal-containing compound, a nitrogen-containing gas, and a hydrogen-gas to deposit a metal nitride layer on a substrate. The metal nitride layer is preferably treated with nitrogen plasma to densify the metal nitride film. The process is preferably carried out in an integrated processing system that generally includes various chambers so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without exposure to possible contaminants.

摘要翻译： 难熔金属层沉积在具有高纵横比的合金或其上形成的通孔的基底上。 接下来，在难熔金属层上沉积等离子体增强CVD难熔金属氮化物层。 然后，在金属氮化物层上沉积金属层。 所得金属层基本上无空隙并具有降低的电阻率，并且具有更大的有效线宽度。 金属氮化物层的等离子体增强化学气相沉积包括形成含金属化合物，含氮气体和氢气的等离子体，以在基板上沉积金属氮化物层。 金属氮化物层优选用氮等离子体处理以使金属氮化物膜致密化。 该方法优选在通常包括各种室的一体化处理系统中进行，使得一旦将基板引入真空环境中，通孔和触点的金属化在不暴露于可能的污染物的情况下发生。

公开(公告)号：US06458684B1

公开(公告)日：2002-10-01

申请号：US09497390

申请日：2000-02-03

申请人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

发明人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

IPC分类号： H01L2144

CPC分类号： C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。 在本发明的一个方面中，在导电部件上形成电介质层。 然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以暴露孔底板上的下面的导电构件。 然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

公开(公告)号：US06355560B1

公开(公告)日：2002-03-12

申请号：US09209434

申请日：1998-12-10

申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

IPC分类号： H01L214763

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

摘要翻译： 本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。 所得到的CVD / PVD金属层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

公开(公告)号：US06207222B1

公开(公告)日：2001-03-27

申请号：US09379696

申请日：1999-08-24

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： B05D512

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US07824743B2

公开(公告)日：2010-11-02

申请号：US11864100

申请日：2007-09-28

申请人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

发明人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

IPC分类号： B05D5/12 ,  H01L21/04 ,  H01L21/203 ,  H05H1/24

CPC分类号： H01J37/34 ,  C23C14/0036 ,  C23C14/0089 ,  C23C14/0641 ,  H01J37/32449 ,  H01J37/32706 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments described herein provide a method for forming two titanium nitride materials by different PVD processes, such that a metallic titanium nitride layer is initially formed by a PVD process in a metallic mode and a titanium nitride retarding layer is formed over a portion of the metallic titanium nitride layer by a PVD process in a poison mode. Subsequently, a first aluminum layer, such as an aluminum seed layer, may be selectively deposited on exposed portions of the metallic titanium nitride layer by a CVD process. Thereafter, a second aluminum layer, such as an aluminum bulk layer, may be deposited on exposed portions of the first aluminum layer and the titanium nitride retarding layer during an aluminum PVD process.

摘要翻译： 本文所述的实施例提供了通过不同PVD工艺形成两种氮化钛材料的方法，使得最初通过金属模式的PVD工艺形成金属氮化钛层，并且在金属钛的一部分上形成氮化钛延迟层 氮化物层通过PVD工艺处于毒液模式。 随后，通过CVD工艺可以在金属氮化钛层的暴露部分上选择性地沉积第一铝层，例如铝籽晶层。 此后，在铝PVD工艺期间，可以在第一铝层和氮化钛延迟层的暴露部分上沉积第二铝层，例如铝本体层。

公开(公告)号：US20060144703A1

公开(公告)日：2006-07-06

申请号：US11029641

申请日：2005-01-05

申请人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

发明人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

IPC分类号： C23C14/00

CPC分类号： H01J37/3408 ,  H01J37/3405

摘要： A multi-track magnetron having a convolute shape and asymmetric about the target center about which it rotates. A plasma track is formed as a closed loop between opposed inner and outer magnetic poles, preferably as two or three radially arranged and spirally shaped counter-propagating tracks with respect to the target center and preferably passing over the rotation axis. The pole shape may be optimized to produce a cumulative track length distribution conforming to the function L=arn. After several iterations of computerized optimization, the pole shape may be tested for sputtering uniformity with different distributions of magnets in the fabricated pole pieces. If the uniformity remains unsatisfactory, the design iteration is repeated with a different n value, different number of tracks, or different pole widths. The optimization reduces azimuthal sidewall asymmetry and improves radial deposition uniformity.

摘要翻译： 具有卷绕形状且围绕其旋转的目标中心不对称的多轨磁控管。 等离子体轨道形成为相对的内部和外部磁极之间的闭合回路，优选地相对于目标中心并且优选地通过旋转轴线而形成为两个或三个径向布置且螺旋形的反向传播轨迹。 极点形状可以被优化以产生符合函数L = ar 的累积轨迹长度分布。 经过数次迭代的计算机化优化，可以测试极点形状，使其在制造的极片中具有不同的磁体分布的溅射均匀性。 如果均匀性不能令人满意，则使用不同的n值，不同数量的轨道或不同的极宽重复设计迭代。 优化可减少方位角侧壁不对称性，提高径向沉积均匀性。

公开(公告)号：US06605531B1

公开(公告)日：2003-08-12

申请号：US09127010

申请日：1998-07-31

申请人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

发明人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

IPC分类号： H01L214763

CPC分类号： H01L21/2855 ,  H01L21/28556 ,  H01L21/76882

摘要： The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.

摘要翻译： 本发明提供了一种通过在基板上沉积不足厚度的金属膜来填充基板上的孔的方法，以填充次半微米孔径，然后在低压室内在低于熔点的温度下将基板退火 沉积金属膜。 本发明还提供了通过在退火膜上物理气相沉积金属膜而在无空隙孔上形成平坦化膜。

公开(公告)号：US06528180B1

公开(公告)日：2003-03-04

申请号：US09577705

申请日：2000-05-23

申请人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

发明人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

IPC分类号： H01L2940

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12611 ,  Y10T428/12743 ,  Y10T428/12806 ,  Y10T428/26

摘要： A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.

摘要翻译： 公开了一种金属化集成电路的方法。 在一个方面，集成电路通过将衬垫材料沉积在衬底上而后接一个或多个金属层进行金属化。 衬垫材料选自钽（Ta），氮化钽（TaN），铌（Nb），氮化铌（NbN），钒（V），氮化钒（VN）及其组合。 优选使用物理气相沉积（PVD）将衬垫材料适当地沉积在衬底上。 使用化学气相沉积（CVD），物理气相沉积（PVD）或CVD和PVD的组合将一个或多个金属层沉积在阻挡层上。