中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

88 records (took 0.022 seconds)

    Static noise margin monitoring circuit and method
    32.
    发明授权
    Static noise margin monitoring circuit and method 有权
    静态噪声容限监控电路及方法

    公开(公告)号：US08729908B2

    公开(公告)日：2014-05-20

    申请号：US13407822

    申请日：2012-02-29

    Applicant: Hayden C. Cranford, Jr. ,  Terence B. Hook

    Inventor： Hayden C. Cranford, Jr. ,  Terence B. Hook

    IPC: G01R29/26

    CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/0409 ,  G11C2029/5002

    Abstract: A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.

    Abstract translation: 一种监视电路和方法，其中具有线性下降沿的电压波形被施加到至少一个测试存储器单元（例如，并联连接的多个测试存储单元）的第一节点。 当在下降沿期间，当测试存储单元的第二个节点处的输出电压上升到高于参考电压时，捕获第一节点处的输入电压。 然后，在捕获的输入电压和（1）第二节点处的输出电压之间确定差异，如在第一节点处的输入电压在下降沿期间低于第一参考电压时捕获的，或者（2） 低参考电压。 该差异与测试存储器单元的静态噪声容限（SNM）成比例，使得通过重复监测指出的差异中的任何变化表示SNM的相应变化。

    Integrated circuit including DRAM and SRAM/logic
    33.
    发明授权
    Integrated circuit including DRAM and SRAM/logic 有权
    集成电路包括DRAM和SRAM /逻辑

    公开(公告)号：US08653596B2

    公开(公告)日：2014-02-18

    申请号：US13344885

    申请日：2012-01-06

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC: H01L21/70 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

    Abstract translation: 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。

    INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
    34.
    发明申请
    INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
    集成电路，包括DRAM和SRAM /逻辑

    公开(公告)号：US20130175595A1

    公开(公告)日：2013-07-11

    申请号：US13344885

    申请日：2012-01-06

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC: H01L27/108 ,  H01L21/336

    CPC classification number: H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

    Abstract translation: 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。

    Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip
    35.
    发明授权
    Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip 有权
    用于在非常薄的绝缘体上（ETSOI）集成电路芯片上控制体偏置的解决方案

    公开(公告)号：US08416009B2

    公开(公告)日：2013-04-09

    申请号：US13181754

    申请日：2011-07-13

    Applicant: Hayden C. Cranford, Jr. ,  Terence B. Hook

    Inventor： Hayden C. Cranford, Jr. ,  Terence B. Hook

    IPC: H01L27/12

    CPC classification number: G05F1/10 ,  H01L27/092 ,  H01L27/1203

    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

    Abstract translation: 公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。 在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压 目标金额。

    SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP
    36.
    发明申请
    SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP 有权
    用于控制超薄型绝缘子（ETSOI）集成电路芯片中的块状偏置电压的解决方案

    公开(公告)号：US20130015911A1

    公开(公告)日：2013-01-17

    申请号：US13181754

    申请日：2011-07-13

    Applicant: Hayden C. Cranford, JR. ,  Terence B. Hook

    Inventor： Hayden C. Cranford, JR. ,  Terence B. Hook

    IPC: G05F1/10 ,  H01L27/12

    CPC classification number: G05F1/10 ,  H01L27/092 ,  H01L27/1203

    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

    Abstract translation: 公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。 在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压 目标金额。

    Pseudo Butted Junction Structure for Back Plane Connection
    38.
    发明申请
    Pseudo Butted Junction Structure for Back Plane Connection 有权
    用于背面连接的伪对接结构

    公开(公告)号：US20120146147A1

    公开(公告)日：2012-06-14

    申请号：US12964082

    申请日：2010-12-09

    Applicant: Terence B. Hook

    Inventor： Terence B. Hook

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78648

    Abstract: Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

    Abstract translation: 在SOI工艺中互连后栅极的对接p-n结，用于制作对接p-n结的方法和设计结构。 对接接头包括通过重叠用于形成后门的离子注入掩模的掩模窗口而在本体衬底中形成的重叠区域。 可以选择性地形成受损区域，以使用用于形成背栅的一个注入掩模，在重叠区域的半导体材料中引入中间间隙能级。 损伤区域使对接接头泄漏并且将重叠的后门导电地耦合到彼此和衬底。 可以形成浮动并且不耦合到衬底的其它后栅。

    Isolated high performance FET with a controllable body resistance
    40.
    发明授权
    Isolated high performance FET with a controllable body resistance 有权
    隔离式高性能FET，具有可控制的体电阻

    公开(公告)号：US07939894B2

    公开(公告)日：2011-05-10

    申请号：US12185368

    申请日：2008-08-04

    Applicant: Terence B. Hook ,  Jenny Hu ,  Jae-Eun Park

    Inventor： Terence B. Hook ,  Jenny Hu ,  Jae-Eun Park

    IPC: H01L21/70

    CPC classification number: H01L27/0738 ,  H01L29/78

    Abstract: The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.

    Abstract translation: 本发明提供了一种控制电气装置中的偏置的方法，包括提供在体半导体衬底上的半导体器件，每个半导体器件包括与相邻器件的有源体区隔离的有源体区域，以及提供与电极接触的体电阻器 活体体区域，其中体电阻器提供半导体器件的体电位的可调节性。 在另一方面，本发明提供了一种半导体器件，其包括体半导体衬底，形成在包括隔离的有源体区域的体半导体衬底上的至少一个场效应晶体管和与隔离的有源体区域电连通的电阻器。

Patent Agency Ranking