公开(公告)号：US20110318942A1

公开(公告)日：2011-12-29

申请号：US13229250

申请日：2011-09-09

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20100285667A1

公开(公告)日：2010-11-11

申请号：US12436459

申请日：2009-05-06

申请人： Griselda Bonilla ,  Satyanarayana V. Nitta ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Satyanarayana V. Nitta ,  Terry A. Spooner

IPC分类号： H01L21/302

CPC分类号： H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material.

摘要翻译： 提供了一种在通过湿蚀刻化学去除损伤层之前，在低k电介质材料的干蚀刻期间恢复低k电介质材料的暴露表面的介电常数，损耗和泄漏的方法。 一旦恢复，电介质材料的表面将不再易于被高度各向异性的湿法蚀刻工艺去除。 然而，湿式蚀刻仍将具有优势，因为它可以去除形成在低k电介质材料中的特征底部的任何蚀刻/灰渣。

公开(公告)号：US07816253B2

公开(公告)日：2010-10-19

申请号：US11308422

申请日：2006-03-23

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Kelly Malone ,  Sanjay Mehta ,  Terry A. Spooner ,  Chih-Chao Yang

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Kelly Malone ,  Sanjay Mehta ,  Terry A. Spooner ,  Chih-Chao Yang

IPC分类号： H01L21/76 ,  H01L21/425 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831

摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

摘要翻译： 当在多孔超低k（ULK）材料上构建互连结构时，沟槽和/或通孔的底部通常被以下金属化工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供在层间电介质（ILD）材料上形成互连结构的方法。 该方法包括处理所述ILD材料的暴露区域以产生致密化区域以及金属化所述致密化区域的步骤。

公开(公告)号：US20090294925A1

公开(公告)日：2009-12-03

申请号：US12538109

申请日：2009-08-08

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L29/06

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20090152723A1

公开(公告)日：2009-06-18

申请号：US11954812

申请日：2007-12-12

申请人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

发明人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/532 ,  H01L21/4763

CPC分类号： C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

摘要翻译： 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。

公开(公告)号：US07528066B2

公开(公告)日：2009-05-05

申请号：US11364953

申请日：2006-03-01

申请人： Chih-Chao Yang ,  Terry A. Spooner ,  Oscar van der Straten

发明人： Chih-Chao Yang ,  Terry A. Spooner ,  Oscar van der Straten

IPC分类号： H01L21/311 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/02063 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.

摘要翻译： 提供一种互连结构，其包括在一个通孔开口的底部的气泡特征及其形成方法。 根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的电介质材料的损伤。 根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。 该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。 根据本发明，这种互连结构是通过在形成线路开口和在所述线路开口中的扩散阻挡层的沉积之前提供通孔开口的底部中的气流特征来实现的。

公开(公告)号：US20090108450A1

公开(公告)日：2009-04-30

申请号：US11928327

申请日：2007-10-30

申请人： James R. LLOYD, JR. ,  Shom Ponoth ,  Terry A. Spooner ,  Chih-Chao Yang

发明人： James R. LLOYD, JR. ,  Shom Ponoth ,  Terry A. Spooner ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of the planarized lower dielectric layer, below the lower cap layer. A lower liner extends into a pattern of the lower cap layer and contacts the copper layer. An upper dielectric layer is on the lower cap layer and a copper layer contacts the lower liner and is formed in a via of at least the lower cap layer. An upper liner is formed over the copper layer, sandwiching the copper layer between the lower liner and the upper liner. An upper copper layer is formed over the upper liner.

摘要翻译： 提供了互连结构及其制造方法。 互连结构是高度可靠的铜互连结构。 互连结构包括在平坦化的下介电层上的平坦化的下介电层和下盖层。 在平坦化的下介电层的沟槽中形成铜材料，在下盖层下方。 下衬垫延伸成下盖层的图案并与铜层接触。 上电介质层在下盖层上，铜层接触下衬垫，并形成在至少下盖层的通孔中。 在铜层之上形成上衬垫，将铜层夹在下衬套和上衬套之间。 在上衬板上方形成上铜层。

公开(公告)号：US07402883B2

公开(公告)日：2008-07-22

申请号：US11380074

申请日：2006-04-25

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/76865

摘要： A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed between two surfaces of a dielectric material, wherein the first liner layer is in direct contact with at least a portion of a conductive wiring material of an underneath interconnect layer; a noble metal layer disposed on the first liner layer at least in the opening; and a conductive wiring material disposed on the noble metal layer, the conductive wiring material substantially filling the opening; wherein the first liner layer, the noble metal layer and the conductive wiring material are coplanar with the two surfaces of the dielectric material of the intermediate interconnect structure, and the noble metal layer includes a different material than the first liner layer.

摘要翻译： 提出了半导体器件的线路（BEOL）结构的后端。 在一个实施例中，该结构可以包括设置在中间互连结构上的第一衬里层，所述中间互连结构具有设置在电介质材料的两个表面之间的开口，其中第一衬垫层与至少一部分 下面的互连层的导电布线材料; 至少在所述开口中设置在所述第一衬垫层上的贵金属层; 以及布置在所述贵金属层上的导电布线材料，所述导电布线材料基本上填充所述开口; 其中所述第一衬里层，所述贵金属层和所述导电布线材料与所述中间互连结构的介电材料的两个表面共面，并且所述贵金属层包括与所述第一衬里层不同的材料。

公开(公告)号：US09059251B2

公开(公告)日：2015-06-16

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08415248B2

公开(公告)日：2013-04-09

申请号：US13474349

申请日：2012-05-17

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。