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    THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT
    31.
    发明申请
    THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT 有权
    通过芯片耦合进行信号传输

    公开(公告)号：US20120122395A1

    公开(公告)日：2012-05-17

    申请号：US12946072

    申请日：2010-11-15

    Applicant: Tzu-Jin YEH ,  Hsieh-Hung HSIEH ,  Jun-De JIN ,  Ming Hsien TSAI ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    Inventor： Tzu-Jin YEH ,  Hsieh-Hung HSIEH ,  Jun-De JIN ,  Ming Hsien TSAI ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC: H04B5/00

    CPC classification number: H04B5/0081

    Abstract: Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

    Abstract translation: 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

    BALANCED TRANSFORMER STRUCTURE
    32.
    发明申请
    BALANCED TRANSFORMER STRUCTURE 审中-公开
    平衡变压器结构

    公开(公告)号：US20120092121A1

    公开(公告)日：2012-04-19

    申请号：US12974080

    申请日：2010-12-21

    Applicant: Jun-De JIN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    Inventor： Jun-De JIN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC: H01F27/28

    CPC classification number: H01L23/5227 ,  H01F2019/085 ,  H01L2924/0002 ,  H03H7/42 ,  H03H2001/0064 ,  H01L2924/00

    Abstract: A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential.

    Abstract translation: 多芯片电子设备包括具有第一端口（P +）和第二端口（P-）的第一绕组。 第一绕组形成在第一芯片的金属层中。 该装置还包括具有第三（S +）和第四端口（S）的第二绕组。 第二绕组形成在第二芯片的金属层中。 第二绕组的中心抽头连接到参考电位。

    JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS
    34.
    发明申请
    JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS 有权
    用于ESD保护射频电路的连接变压器

    公开(公告)号：US20110233678A1

    公开(公告)日：2011-09-29

    申请号：US12731562

    申请日：2010-03-25

    Applicant: Ming-Hsien TSAI ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    Inventor： Ming-Hsien TSAI ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC: H01L29/93 ,  H01L27/06 ,  H01L23/60

    CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

    Abstract translation: ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

    Inductor Q value improvement
    35.
    发明申请
    Inductor Q value improvement 有权
    电感Q值改善

    公开(公告)号：US20050023639A1

    公开(公告)日：2005-02-03

    申请号：US10632456

    申请日：2003-07-31

    Applicant: Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

    Inventor： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

    IPC: H01L21/02 ,  H01L27/08 ,  H01L29/00

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

    Abstract translation: 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

    Power cell and power cell circuit for a power amplifier
    36.
    发明授权
    Power cell and power cell circuit for a power amplifier 有权

    公开(公告)号：US09780211B2

    公开(公告)日：2017-10-03

    申请号：US13731873

    申请日：2012-12-31

    Applicant: Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

    Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Chia-Chung Chen

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66901

    Abstract: A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin.

    INTEGRATED PASSIVE DEVICE FILTER WITH FULLY ON-CHIP ESD PROTECTION
    39.
    发明申请
    INTEGRATED PASSIVE DEVICE FILTER WITH FULLY ON-CHIP ESD PROTECTION 有权
    集成无源器件滤波器，具有全面的片上ESD保护功能

    公开(公告)号：US20140036396A1

    公开(公告)日：2014-02-06

    申请号：US13562571

    申请日：2012-07-31

    Applicant: Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

    IPC: H02H9/04 ,  H05K13/00 ,  H03H7/01

    CPC classification number: H03H7/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/64 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  Y10T29/49117 ,  H01L2924/00

    Abstract: The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.

    Abstract translation: 本公开涉及可以重用于各种集成电路（IC）应用的片上静电放电（ESD）保护电路。 电感 - 电容（LC）并联谐振器和并联电感（连接到地）均用作ESD保护电路，也可用作给定IC应用的阻抗匹配网络的一部分。 ESD LC谐振器可以设计有各种带通滤波器（BPF）拓扑。 片上ESD保护电路允许同时优化ESD和BPF性能，用于集成无源器件（IPD）工艺的完全片上ESD解决方案，无需主动ESD器件保护，另外还支持片外ESD保护 保护，降低功耗，并创建可重用的BPF拓扑。

    On-chip ferrite bead inductor
    40.
    发明授权
    On-chip ferrite bead inductor 有权
    片上铁氧体磁珠电感

    公开(公告)号：US08618631B2

    公开(公告)日：2013-12-31

    申请号：US13372873

    申请日：2012-02-14

    Applicant: Jun-De Jin ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Tzu-Jin Yeh

    IPC: H01L27/08 ,  H01L29/66 ,  H01L21/00

    CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

    Abstract translation: 一种具有原位芯片级铁氧体磁珠电感器的半导体结构及其形成方法。 实施例包括基板，形成在基板上的第一介电层，形成在第一介电层上的下铁氧体层，以及与该结构中的下铁氧体层间隔开的上铁氧体层。 第一金属层可以形成在下铁素体层上方，第二金属层形成在上铁氧体层下面，其中至少第一或第二金属层具有包括多匝的线圈构型。 至少一个第二电介质层可以设置在第一和第二金属层之间。 铁氧体磁珠电感器具有小的外形尺寸，并且可以使用BEOL工艺来形成。

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