公开(公告)号：US08164504B2

公开(公告)日：2012-04-24

申请号：US12882421

申请日：2010-09-15

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/0678 ,  H03M1/0682 ,  H03M1/468

摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2V-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

摘要翻译： 逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2V-1，第二转换单元，被配置为与第一转换单元差分地操作 ，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为将比较器的输出电压接收到 将接收到的输出电压转换成数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并且使用校正电容器阵列的校正数字信号来校正位电容器阵列的数字信号 接收数字信号。

公开(公告)号：US08063961B2

公开(公告)日：2011-11-22

申请号：US12195194

申请日：2008-08-20

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H04N3/14 ,  H04N5/335 ,  G11C27/02 ,  H03K5/00 ,  H03K17/00

CPC分类号： H03F3/45973 ,  H03F1/02 ,  H03F3/005 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45514 ,  H04N5/335 ,  H04N5/378

摘要： Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array.

摘要翻译： 提供了具有共享放大器的双采样/像素增益放大器（CDS / PxGA）电路，更具体地，涉及用于基于电容调整放大器的增益的双CDS / PxGA电路。 双CDS / PxGA电路包括：用于对第一像素的复位电平和数据电平进行采样的第一采样器; 第二采样器，用于对第二像素的复位电平和数据电平进行采样; 以及运算放大器，用于从第一和第二采样器接收采样值，使用采样值来计算第一和第二像素的输出信号，并放大所计算的输出信号。 因此，可以通过使用双CDS / PxGA结构来降低运算放大器的速度，通过共享运算放大器来降低功耗，并且通过使用电容器阵列调整电容来获得宽范围的可变增益。

公开(公告)号：US20110227774A1

公开(公告)日：2011-09-22

申请号：US12882421

申请日：2010-09-15

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/12

CPC分类号： H03M1/0678 ,  H03M1/0682 ,  H03M1/468

摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2ν-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

摘要翻译： 逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2＆ngr; -1，第二转换单元，被配置为与第一转换差分地操作 单元，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为接收比较器的输出电压 将所接收的输出电压转换为数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并使用校正电容阵列的校正数字信号校正位电容阵列的数字信号 接收数字信号。

公开(公告)号：US07978117B2

公开(公告)日：2011-07-12

申请号：US12539406

申请日：2009-08-11

申请人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Deuk Jeon ,  Young Kyun Cho ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/34

CPC分类号： H03M1/164 ,  H03M1/1215 ,  H03M1/468 ,  H03M1/804

摘要： A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

摘要翻译： 提供了多级双逐次逼近寄存器模数转换器（SAR ADC）和使用其进行模数转换的方法。 多级双SAR ADC包括：多个SAR ADC级，用于将模拟输入电压转换为预定位数字信号，每个SAR ADC级串联连接并包括两个SAR ADC; 和分别连接在每两个连续的SAR ADC级之间的至少一个残余放大器，放大从先前的SAR ADC级输出的剩余电压，以将放大的残余电压输出到下一个SAR ADC级。 前一个SAR ADC级的两个SAR ADC共享残留放大器。

公开(公告)号：US07893860B2

公开(公告)日：2011-02-22

申请号：US12472375

申请日：2009-05-27

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/069 ,  H03M1/0607 ,  H03M1/468 ,  H03M1/804

摘要： A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

摘要翻译： 提供逐次逼近寄存器（SAR）模数转换器（ADC）及其驱动方法。 SAR ADC包括：第一转换单元，包括与位数相对应的位电容阵列和校正电容器阵列;比较器，根据转换单元的输出电压输出对应于每个电容器的高电压或低电压;以及校正 单元根据比较器的高或低输出中的校正电容器阵列的输出校正位电容器的输出。 因此，具有与最低有效位（LSB）相同的电容的两个位使得能够校正数字输出误差，使得信号转换器的无杂散动态范围（SFDR）增加，并且信噪比和失真比 （SNDR）的输出信号得到改善。

公开(公告)号：US20110032134A1

公开(公告)日：2011-02-10

申请号：US12773768

申请日：2010-05-04

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Jae Won Nam ,  Jong Kee Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/682 ,  H03M1/804 ,  H03M1/806

摘要： A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching.

摘要翻译： 提供了数模转换器（DAC）。 DAC包括正转换器，负转换器和用于接收正转换器和负转换器的输出的比较器，将输出与参考电压进行比较，并产生输出电压。 正转换器和负转换器中的每个包括具有对应于各高位的多个位电容器的高位转换器，包括对应于各低位的多个位电容器的低位转换器和用于连接的耦合电容器 低位转换器与低位转换器串联。 正转换器和负转换器中的每一个在转换各个位时接收偏置电压以具有均匀的偏移。 因此，可以使用小面积获得高分辨率。 此外，可以减少电容器的数量，并且可以使单位电容器的电容最大化。 因此，可以最小化热噪声和器件不匹配。

公开(公告)号：US20100019321A1

公开(公告)日：2010-01-28

申请号：US12556666

申请日：2009-09-10

申请人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

发明人： Young Kyun CHO ,  Tae Moon ROH ,  Jong Dae KIM

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US20090327380A1

公开(公告)日：2009-12-31

申请号：US11731927

申请日：2007-04-02

申请人： Young-Kyun Cho

发明人： Young-Kyun Cho

IPC分类号： G06F7/58

CPC分类号： G06F7/588

摘要： A circuit that generates a random number includes a phase-locked loop circuit and a sampling circuit. The phase-locked loop circuit generates an internal clock signal that is synchronized with a reference signal in which the internal clock has a random noise. The sampling circuit samples the reference signal in response to the internal clock signal to generate a random data bit. The circuit of generating a random number is capable of generating a random number with high randomness and is capable of operating at a relatively low frequency.

摘要翻译： 产生随机数的电路包括锁相环电路和采样电路。 锁相环电路产生与内部时钟具有随机噪声的参考信号同步的内部时钟信号。 采样电路响应于内部时钟信号对参考信号进行采样以产生随机数据位。 产生随机数的电路能够产生具有高随机性的随机数并能够以较低的频率工作。

公开(公告)号：US20090086072A1

公开(公告)日：2009-04-02

申请号：US12195194

申请日：2008-08-20

申请人： Young Kyun Cho ,  Young Deuk Jeon ,  Chong Ki Kwon ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Young Deuk Jeon ,  Chong Ki Kwon ,  Jong Dae Kim

IPC分类号： H04N3/14 ,  H03F1/02 ,  H03K17/00

CPC分类号： H03F3/45973 ,  H03F1/02 ,  H03F3/005 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45514 ,  H04N5/335 ,  H04N5/378

摘要： Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array.

摘要翻译： 提供了具有共享放大器的双采样/像素增益放大器（CDS / PxGA）电路，更具体地，涉及用于基于电容调整放大器的增益的双CDS / PxGA电路。 双CDS / PxGA电路包括：用于对第一像素的复位电平和数据电平进行采样的第一采样器; 第二采样器，用于对第二像素的复位电平和数据电平进行采样; 以及运算放大器，用于从第一和第二采样器接收采样值，使用采样值来计算第一和第二像素的输出信号，并放大所计算的输出信号。 因此，可以通过使用双CDS / PxGA结构来降低运算放大器的速度，通过共享运算放大器来降低功耗，并且通过使用电容器阵列调整电容来获得宽范围的可变增益。

公开(公告)号：US07375557B2

公开(公告)日：2008-05-20

申请号：US11314087

申请日：2005-12-22

申请人： Young-Kyun Cho

发明人： Young-Kyun Cho

IPC分类号： G01R25/00 ,  H03D13/00

CPC分类号： H03L7/0891 ,  H03D13/004 ,  H03L7/0895

摘要： The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.

摘要翻译： 相位频率检测器可以包括被配置为产生第一信号的第一触发器，第一信号响应于第一输入信号的第一边沿而转换到第一逻辑电平，并且响应于第一信号转换到第二逻辑电平 延迟复位信号和第二触发器，其被配置为产生第二信号，所述第二信号响应于第二输入信号的第二边沿而转变到第一逻辑电平，并且响应于延迟的复位信号而转变到第二逻辑电平 。 相位频率检测器还可以包括第一延迟单元，其被配置为延迟复位信号以产生延迟的复位信号;以及第二延迟单元，其被配置为延迟复位信号以产生输出控制信号，用于调整第一和第 第二信号。