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    POWER MANAGEMENT TECHNIQUES
    33.
    发明申请
    POWER MANAGEMENT TECHNIQUES 有权

    公开(公告)号：US20170322614A1

    公开(公告)日：2017-11-09

    申请号：US15150109

    申请日：2016-05-09

    Applicant: Apple Inc.

    Inventor： Peter F. Holland ,  Hao Chen ,  Sukalpa Biswas

    IPC: G06F1/32 ,  G06T1/20 ,  G09G5/00 ,  G06T1/60

    CPC classification number: G06F1/3265 ,  G06F1/3218 ,  G06F1/3225 ,  G09G5/006 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2340/06 ,  G09G2360/121

    Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.

    DISPLAY POWER MANAGEMENT
    34.
    发明申请
    DISPLAY POWER MANAGEMENT 有权
    显示电源管理

    公开(公告)号：US20140232731A1

    公开(公告)日：2014-08-21

    申请号：US13773522

    申请日：2013-02-21

    Applicant: APPLE INC.

    Inventor： Peter Holland ,  Hao Chen ,  Albert Kuo

    IPC: G06T1/60

    CPC classification number: G06T1/60 ,  G06F1/3228 ,  G06F1/3265 ,  G06F1/3287 ,  G06T3/4007 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2340/045 ,  G09G2360/127 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.

    Abstract translation: 公开了与集成电路内的电源管理有关的技术。 在一个实施例中，显示缓冲器通过数据传输互连接收图像数据。 基于接收到的图像数据大于阈值数据量，数据传输互连被断电。 显示缓冲器将图像数据的至少一部分发送到一个或多个输出，并且响应于发送，数据传输互连被加电。 在一些实施例中，显示缓冲器包括多个行缓冲器，每个行缓冲器被配置为存储相应的图像源线。 在这样的实施例中，被配置为使得要显示的图像的显示管道包括显示缓冲器，并且响应于包括两个或更多个图像源线的接收图像数据执行掉电。

    QoS-aware scheduling
    35.
    发明授权
    QoS-aware scheduling 有权

    公开(公告)号：US08553042B2

    公开(公告)日：2013-10-08

    申请号：US13653109

    申请日：2012-10-16

    Applicant: Apple Inc.

    Inventor： Sukalpa Biswas ,  Hao Chen

    IPC: G09G5/39

    CPC classification number: G06F9/5033 ,  G06F13/1668

    Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

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