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    Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
    32.
    发明授权
    Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N 有权
    在N位/单元模拟存储单元器件中以M位/单元密度存储，M> N

    公开(公告)号：US08964466B2

    公开(公告)日：2015-02-24

    申请号：US14264303

    申请日：2014-04-29

    Applicant: Apple Inc.

    Inventor： Ofir Shalvi ,  Naftali Sommer ,  Uri Perlmutter ,  Dotan Sokolov

    IPC: G11C16/04 ,  G06F11/10 ,  G11C11/56 ,  G11C27/00 ,  G11C16/26

    CPC classification number: G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5641

    Abstract: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

    Abstract translation: 一种用于数据存储的方法包括接收用于存储在包括多个模拟存储器单元的存储器中的数据，并且支持一组内置的编程命令。 每个编程命令在存储器单元的子集中编写从一组N页中选择的相应页面。 存储器单元的子集被编程为通过执行仅从集合中绘制的编程命令的序列来存储数据的M页M> N。

    Error correction codes for incremental redundancy
    33.
    发明授权
    Error correction codes for incremental redundancy 有权
    增量冗余的纠错码

    公开(公告)号：US08954831B2

    公开(公告)日：2015-02-10

    申请号：US14336066

    申请日：2014-07-21

    Applicant: Apple Inc.

    Inventor： Micha Anholt ,  Naftali Sommer

    IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1012 ,  H03M13/114 ,  H03M13/118 ,  H03M13/6393

    Abstract: A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations.

    Abstract translation: 一种方法包括接受输入，该输入包括已由由奇偶校验方程组确定的ECC编码的码字的至少一部分。 码字包括数据位和奇偶校验位。 使用数据位和仅输入中的奇偶校验位的第一部分子集，并且仅使用方程的第二部分子集，将解码处理应用于码字。 在使用部分子集解码码字失败时，使用输入中的数据位和所有奇偶校验位，并使用所有方程对码字进行重新解码。 定义奇偶校验方程组，使得码字中的任何奇偶校验位出现在多个等式中，并且奇偶校验位的第一部分子集中的任何奇偶校验位出现在等式的第二部分子集中的多个等式中。

    UNEVEN WEAR LEVELING IN ANALOG MEMORY DEVICES
    34.
    发明申请
    UNEVEN WEAR LEVELING IN ANALOG MEMORY DEVICES 有权
    在模拟记忆体设备中耐磨损

    公开(公告)号：US20150012686A1

    公开(公告)日：2015-01-08

    申请号：US13935746

    申请日：2013-07-05

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Shai Ojalvo ,  Yoav Kasorla ,  Naftali Sommer

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7211

    Abstract: A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme.

    Abstract translation: 一种用于在包括多个模拟存储器单元的存储器中的数据存储的方法，包括基于所述存储器单元的特性定义不均匀磨损平衡方案，所述不均匀磨损均衡方案以相应不同的第一方式来编程和擦除所述存储器单元的至少第一和第二子集 和第二个编程和擦除（P / E）率。 根据不均匀的磨损均衡方案将数据存储在存储器中。

    Independent Management of Data and Parity Logical Block Addresses
    35.
    发明申请
    Independent Management of Data and Parity Logical Block Addresses 审中-公开
    数据和奇偶校验逻辑块地址的独立管理

    公开(公告)号：US20140365821A1

    公开(公告)日：2014-12-11

    申请号：US14468527

    申请日：2014-08-26

    Applicant: Apple Inc.

    Inventor： Avraham Poza Meir ,  Oren Golov ,  Naftali Sommer ,  Moshe Neerman

    IPC: G06F11/10

    CPC classification number: G06F11/108 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/1096 ,  G06F12/0246 ,  G06F12/06 ,  G06F2211/1059 ,  G06F2212/7205

    Abstract: A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas.

    Abstract translation: 数据存储方法包括在与存储在存储器中的各个逻辑地址相关联的一组数据项中识别与包含应用数据的数据项相关联的逻辑地址的第一子集，以及与包含应用数据的逻辑地址相关联的第二子集 包含已经通过应用数据计算的奇偶校验信息的数据项。 与第一识别的子集相关联的数据项存储在存储器的一个或多个第一物理存储器区域中，并且与第二识别的子集相关联的数据项存储在存储器的一个或多个第二物理存储器区域中，不同于 第一个物理内存区域。 在第一物理存储器区域和第二物理存储器区域中独立地执行存储器管理任务。

    SELECTIVE RE-PROGRAMMING OF ANALOG MEMORY CELLS
    36.
    发明申请
    SELECTIVE RE-PROGRAMMING OF ANALOG MEMORY CELLS 审中-公开
    模拟记忆细胞的选择性重新编程

    公开(公告)号：US20140340965A1

    公开(公告)日：2014-11-20

    申请号：US14336054

    申请日：2014-07-21

    Applicant: Apple Inc.

    Inventor： Naftali Sommer ,  Uri Perlmutter ,  Shai Winter

    IPC: G11C16/10 ,  G11C29/00 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3459 ,  G11C29/78

    Abstract: A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states. After initially storing the data, a second group of the analog memory cells, which potentially cause interference to the first group, is programmed. After programming the second group, the first group is selectively re-programmed with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset.

    Abstract translation: 一种用于数据存储的方法包括在包括多个模拟存储器单元的存储器中定义擦除状态，一组未擦除的编程状态和未擦除编程状态的部分子集。 最初将数据存储在第一组模拟存储器单元中，通过将第一组中的至少一些存储单元中的每一个从擦除状态编程为从非擦除编程状态集合中选择的各自的非擦除编程状态 。 在最初存储数据之后，编程可能对第一组产生干扰的第二组模拟存储器单元。 在对第二组进行编程之后，通过重复仅对其各自编程状态属于部分子集的第一组中的存储器单元进行编程，对该第一组进行有选择地重新编程。

    ENHANCED DATA STORAGE IN 3-D MEMORY USING STRING-SPECIFIC SOURCE-SIDE BIASING
    37.
    发明申请
    ENHANCED DATA STORAGE IN 3-D MEMORY USING STRING-SPECIFIC SOURCE-SIDE BIASING 有权
    3-D存储器中的数据存储增强使用特定的源极偏置

    公开(公告)号：US20140313832A1

    公开(公告)日：2014-10-23

    申请号：US13865351

    申请日：2013-04-18

    Applicant: APPLE INC.

    Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

    Abstract translation: 一种方法包括将数据存储在存储器中，其包括以具有与位线相关联的第一维度的三维（3-D）配置布置的多个模拟存储器单元串，与字线相关联的第二维度和与第三维度相关联的第三维度 具有部分，使得每个字符串与相应的位线和相应的部分相关联，并且包括连接到各个字线的多个存储器单元。 对于一组字符串，对组中字符串的属性的各个值进行评估。 根据属性的各个值，针对组中的各个串来计算源侧电压，并且组中的串的各个源侧被相应的源极侧电压偏置。 当串被相应的源侧电压偏置时，对组中的串执行存储器操作。

    Memory device with internal signal processing unit
    38.
    发明授权
    Memory device with internal signal processing unit 有权
    内存信号处理单元

    公开(公告)号：US08788906B2

    公开(公告)日：2014-07-22

    申请号：US13860211

    申请日：2013-04-10

    Applicant: Apple Inc.

    Inventor： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    IPC: G11C23/00 ,  G06F12/00 ,  G06F11/10 ,  G11C11/56

    CPC classification number: G06F11/1072 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G11C11/56 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004

    Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.

    Abstract translation: 一种用于操作存储器的方法包括：通过将输入存储值写入到一组模拟存储器单元中，将数据存储在制造在第一半导体管芯上的多个模拟存储器单元中。 在存储数据之后，使用相应的不同的阈值集合读取组中每个模拟存储器单元的多个输出存储值，从而提供分别对应于阈值集合的输出存储值的多个输出组。 输出存储值的多个输出组由在第一半导体管芯上制造的电路预处理，以产生预处理的数据。 预处理数据被提供给存储器控制器，该存储器控制器制造在与第一半导体管芯不同的第二半导体管芯上。 以使得存储器控制器能够响应于预处理的数据重构数据。

    SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS
    39.
    发明申请
    SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS 审中-公开
    模拟记忆体阵列中编程方案的选择性激活

    公开(公告)号：US20140201433A1

    公开(公告)日：2014-07-17

    申请号：US14215208

    申请日：2014-03-17

    Applicant: Apple Inc.

    Inventor： Dotan Sokolov ,  Naftali Sommer ,  Uri Perlmutter ,  Ofir Shalvi

    IPC: G11C27/00

    CPC classification number: G11C27/005 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/3418

    Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.

    Abstract translation: 一种用于数据存储的方法包括：定义第一编程方案，其编程一组模拟存储器单元，同时减少由与该组相邻的至少一个存储器单元引起的干扰;以及第二编程方案，其对该组模拟存储器单元进行编程 不能减少第一编程方案减少的所有干扰。 基于针对模拟存储器单元定义的标准来选择第一和第二编程方案之一。 使用所选择的编程方案将数据存储在模拟存储器单元的组中。

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