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公开(公告)号：US20120228736A1
公开(公告)日：2012-09-13
申请号：US13474790
申请日：2012-05-18
申请人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
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32.发明授权Technique to create a buried plate in embedded dynamic random access memory device 有权在嵌入式动态随机存取存储器件中创建掩埋板的技术公开(公告)号：US08236710B2
公开(公告)日：2012-08-07
申请号：US12899638
申请日：2010-10-07
申请人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
发明人： Ashima B. Chakravarti , Jacob B. Dadson , Paul J. Higgins , Babar A. Khan , John J. Moore , Christopher C. Parks , Rohit S. Takalkar
IPC分类号： H01L21/76
CPC分类号： H01L27/10867 , H01L29/66181 , H01L29/945 , Y10S438/957
摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
摘要翻译： 为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。 在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。 然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。
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公开(公告)号：US08080451B2
公开(公告)日：2011-12-20
申请号：US12684551
申请日：2010-01-08
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Solutions for fabricating a semiconductor structure. One embodiment includes a method for fabricating a semiconductor structure, the method including: forming a first dielectric structure on a substrate, the first dielectric structure including silicon nitride (Si3N4); forming a second dielectric structure in proximity to the first dielectric structure; and growing a non-epitaxial thin film from a surface of the first dielectric structure; wherein the growing includes using a combination of precursor, carrier and etchant with a ratio among the precursor, carrier, and etchant being adjusted for selective growth of the thin film on the surface, and wherein the thin film includes one selected from a group consisting of: a monocrystalline material, an amorphous material, a polycrystalline material and a combination thereof.
摘要翻译： 制造半导体结构的解决方案。 一个实施例包括一种用于制造半导体结构的方法，所述方法包括：在衬底上形成第一电介质结构，所述第一电介质结构包括氮化硅（Si 3 N 4）; 在所述第一电介质结构附近形成第二电介质结构; 以及从所述第一电介质结构的表面生长非外延薄膜; 其中所述生长包括使用前体，载体和蚀刻剂的组合，前体，载体和蚀刻剂之间的比例被调节用于表面上的薄膜的选择性生长，并且其中所述薄膜包括选自以下的一种： ：单晶材料，非晶材料，多晶材料及其组合。
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公开(公告)号：US07687804B2
公开(公告)日：2010-03-30
申请号：US11970592
申请日：2008-01-08
IPC分类号： H01L29/04 , H01L31/20 , H01L31/036 , H01L31/0376
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译： 制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。
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公开(公告)号：US20080026516A1
公开(公告)日：2008-01-31
申请号：US11459730
申请日：2006-07-25
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
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36.发明授权Polycrystalline silicon layer with nano-grain structure and method of manufacture 失效具有纳米晶粒结构的多晶硅层及其制造方法公开(公告)号：US07232774B2
公开(公告)日：2007-06-19
申请号：US10707878
申请日：2004-01-20
申请人： Ashima B. Chakravarti , Bruce B. Doris , Romany Ghali , Oleg G. Gluschenkov , Michael A. Gribelyuk , Woo-Hyeong Lee , Anita Madan
发明人： Ashima B. Chakravarti , Bruce B. Doris , Romany Ghali , Oleg G. Gluschenkov , Michael A. Gribelyuk , Woo-Hyeong Lee , Anita Madan
IPC分类号： H01L21/00
CPC分类号： C23C16/24 , C23C16/46 , H01L21/28035 , H01L21/32055 , H01L29/4925
摘要： A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.
摘要翻译： 形成超小晶粒尺寸的多晶硅的方法采用CVD装置的衬底的上侧和下侧的差分加热，其中衬底的下侧比上侧受到明显更多的功率，优选大于 75％的权力; 并且其中在超过550℃的硅结晶温度超过50℃的温度下在沉积期间保持基底。
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公开(公告)号：US06528383B1
公开(公告)日：2003-03-04
申请号：US10016016
申请日：2001-12-12
IPC分类号： H01L2100
CPC分类号： H01L27/10894 , H01L27/0676 , H01L27/0802 , H01L27/10861 , H01L28/20 , H01L28/40
摘要： A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.
摘要翻译： 使用与形成用于DRAM单元的沟槽电容器相同的步骤中的许多步骤，在集成电路中形成紧凑型电阻器; 特别是在掺杂衬底以形成用于电容器的底板的步骤之后在沟槽内部沉积重掺杂的锗层，在沟槽中沉积具有所需电阻率的多晶硅，然后除去锗并仅留下足以形成欧姆 接触沟槽底部。
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公开(公告)号：US5643640A
公开(公告)日：1997-07-01
申请号：US563165
申请日：1995-11-27
CPC分类号： C03C3/112 , C23C16/401
摘要： A fluorinated phosphosilicate glass (FPSG) is produced in a plasma-enhanced chemical vapor deposition process (PECVD) in which the plasma source comprises conventional phosphosilicate glass-forming materials together with one or more fluorine gas-forming materials. The deposited fluorine-gas enhances the filling of gaps or voids with dielectric glass compositions by etching the top of the via holes or gaps during the filling operation. The present fluorine-doped phosphosilicate glass compositions are stable compared to conventional phosphosilicate glass compositions which are relatively unstable and unsatisfactory for use as gap-filling dielectric glass compositions.
摘要翻译： 在等离子体增强化学气相沉积工艺（PECVD）中生产氟化磷硅酸盐玻璃（FPSG），其中等离子体源包含常规的磷硅酸盐玻璃形成材料以及一种或多种氟气形成材料。 沉积的氟气通过在填充操作期间蚀刻通孔或间隙的顶部来增强用电介质玻璃组合物填充间隙或空隙。 本发明的氟掺杂磷硅酸盐玻璃组合物与常规的磷硅酸盐玻璃组合物相比是稳定的，这些组合物相对不稳定并且不能令人满意地用作间隙填充电介质玻璃组合物。
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公开(公告)号：US08105955B2
公开(公告)日：2012-01-31
申请号：US11464664
申请日：2006-08-15
IPC分类号： H01L21/31
CPC分类号： H01L29/78 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L29/1054
摘要： An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.
摘要翻译： 集成电路系统包括衬底，衬底上的含碳的硅区域，衬底上的非含碳的硅区域和包含非含碳硅区域和碳 - 碳区域的硅 - 碳区域， 含硅区域。
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公开(公告)号：US20100009524A1
公开(公告)日：2010-01-14
申请号：US12168945
申请日：2008-07-08
申请人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
发明人： Ashima B. Chakravarti , Judson Robert Holt , Jeremy John Kempisty , Suk Hoon Ku , Woo-Hyeong Lee , Amlan Majumdar , Ryan Matthew Mitchell , Renee Tong Mo , Zhibin Ren , Dinkar Singh
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/302 , H01L21/30604 , Y10S438/947 , Y10S438/977
摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate.
摘要翻译： 半导体制造方法。 该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。 接下来，去除半导体衬底的顶部。 接下来，在半导体衬底上外延生长第一半导体层，其中第一半导体层中的半导体材料的第一原子百分数等于半导体衬底中半导体材料的一定原子百分数。
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