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公开(公告)号：US20230384947A1
公开(公告)日：2023-11-30
申请号：US18208639
申请日：2023-06-12
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Joseph L. Greathouse , Alan D. Smith , Francisco L. Duran , Felix Kuehling , Anthony Asaro
CPC classification number: G06F3/0619 , G06F3/064 , G06F12/0607 , G06F3/0659 , G06F3/0673 , G06F3/0644
Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
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公开(公告)号：US11604737B1
公开(公告)日：2023-03-14
申请号：US17516860
申请日：2021-11-02
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Joseph L. Greathouse , Steven Tony Tye , Mark Fowler , Milind N. Nemlekar
IPC: G06F12/00 , G06F12/0891 , G06F12/0831 , G06F9/448 , G06F9/30 , G06F12/0888
Abstract: A processing device determines a scope indicating at least a portion of the processing system and target data from atomic memory operation to be performed. Based on the scope, the processing device determines one or more hardware parameters for at least a portion of the processing system. The processing device then compares the hardware parameters to the scope and target data to determine one or more corrections. The processing device then provides the scope, target data, hardware parameters, and corrections to a plurality of hardware lookup tables. The hardware lookup tables are configured to receive the scope, target data, hardware parameters, and corrections as inputs and output values indicating one or more coherency actions and one or more orderings. The processing device then executes one or more of the indicated coherency actions and the atomic memory operation based on the indicated ordering.
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公开(公告)号：US11556162B2
公开(公告)日：2023-01-17
申请号：US15923153
申请日：2018-03-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Shijia Wei , Joseph L. Greathouse , John Kalamatianos
Abstract: A processor utilizes instruction based sampling to generate sampling data sampled on a per instruction basis during execution of an instruction. The sampling data indicates what processor hardware was used due to the execution of the instruction. Software receives the sampling data and generates an estimate of energy used by the instruction based on the sampling data. The sampling data may include microarchitectural events and the energy estimate utilizes a base energy amount corresponding to the instruction executed along with energy amounts corresponding to the microarchitectural events in the sampling data. The sampling data may include switching events associated with hardware blocks that switched due to execution of the instruction and the energy estimate for the instruction is based on the switching events and capacitance estimates associated with the hardware blocks.
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Patent Agency Ranking
公开(公告)号：US20190286209A1
公开(公告)日：2019-09-19
申请号：US15923153
申请日：2018-03-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Shijia Wei , Joseph L. Greathouse , John Kalamatianos
IPC: G06F1/32
Abstract: A processor utilizes instruction based sampling to generate sampling data sampled on a per instruction basis during execution of an instruction. The sampling data indicates what processor hardware was used due to the execution of the instruction. Software receives the sampling data and generates an estimate of energy used by the instruction based on the sampling data. The sampling data may include microarchitectural events and the energy estimate utilizes a base energy amount corresponding to the instruction executed along with energy amounts corresponding to the microarchitectural events in the sampling data. The sampling data may include switching events associated with hardware blocks that switched due to execution of the instruction and the energy estimate for the instruction is based on the switching events and capacitance estimates associated with the hardware blocks.
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公开(公告)号：US09990203B2
公开(公告)日：2018-06-05
申请号：US14981310
申请日：2015-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Leonardo de Paula Rosa Piga , Abhinandan Majumdar , Indrani Paul , Wei Huang , Manish Arora , Joseph L. Greathouse
IPC: G06F9/30
CPC classification number: G06F9/30192 , G06F9/30014 , G06F9/30083 , G06F9/30145 , G06F11/00
Abstract: Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.
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公开(公告)号：US20180143781A1
公开(公告)日：2018-05-24
申请号：US15360518
申请日：2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , Christopher D. Erb , Michael G. Collins
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0656 , G06F3/0685 , G06F9/4443 , G06F9/451 , G06T1/20 , G06T1/60
Abstract: A processing apparatus is provided that includes a plurality of memory regions each corresponding to a memory address and configured to store data associated with the corresponding memory address. The processing apparatus also includes an accelerated processing device in communication with the memory regions and configured to determine a request to allocate an initial memory buffer comprising a number of contiguous memory regions, create a new memory buffer comprising one or more additional memory regions adjacent to the contiguous memory regions of the initial memory buffer, assign one or more values to the one or more additional memory regions and detect a change to the one or more values at the one or more additional memory regions.
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公开(公告)号：US09448909B2
公开(公告)日：2016-09-20
申请号：US14054345
申请日：2013-10-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , David S. Christie
CPC classification number: G06F11/3466 , G06F11/3409 , G06F11/348 , G06F11/3636 , G06F2201/865 , G06F2201/88
Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. When the processor processes a given instruction of a given instruction type, the processor updates a corresponding performance counter. When the performance counter reaches a threshold, the processor generates an interrupt and compares a location of the given instruction with stored locations in a given list. If a match is not found, then the processor processes an instruction following the given instruction in the computer program without processing intermediate instrumentation code. If a match is found, then the processor processes instrumentation code. Regardless of whether or not the instrumentation code is processed, when control flow returns to the computer program, the corresponding performance counter is initialized with a random value.
Abstract translation: 一种有效执行程序仪表的系统和方法。 处理器处理存储在存储器中的指令。 当处理器处理给定指令类型的给定指令时，处理器更新相应的性能计数器。 当性能计数器达到阈值时，处理器产生中断，并将给定指令的位置与给定列表中存储的位置进行比较。 如果未找到匹配项，则处理器处理计算机程序中的给定指令之后的指令，而不处理中间的仪器代码。 如果找到匹配项，则处理器处理检测代码。 无论仪器代码是否被处理，当控制流程返回到计算机程序时，相应的性能计数器将以随机值初始化。
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公开(公告)号：US20150304177A1
公开(公告)日：2015-10-22
申请号：US14255137
申请日：2014-04-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Joseph L. Greathouse , Indrani Paul
CPC classification number: H04L43/04 , H04L41/5009 , H04L41/5096 , H04L43/08
Abstract: Application performance data that indicates a level of service provided in executing one or more applications is determined in software running on one or more processor cores in a computing system that executes the one or more applications. The application performance data is provided to a controller in the computing system that is distinct from the one or more processor cores.
Abstract translation: 指示在执行一个或多个应用程序中提供的服务级别的应用程序性能数据在运行在执行一个或多个应用程序的计算系统中的一个或多个处理器核心上的软件中确定。 将应用性能数据提供给不同于一个或多个处理器核心的计算系统中的控制器。
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