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公开(公告)号：US20150102429A1
公开(公告)日：2015-04-16
申请号：US14576111
申请日：2014-12-18
申请人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L29/04 , H01L21/308 , H01L29/78
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
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公开(公告)号：US20140239258A1
公开(公告)日：2014-08-28
申请号：US13571657
申请日：2012-08-10
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
摘要翻译： 隧道场效应晶体管（TFET）包括源区，源区包括纳米线的第一部分; 沟道区，所述沟道区包括纳米线的第二部分; 漏极区域，所述漏极区域包括硅衬垫的一部分，所述硅衬垫位于所述沟道区域附近; 以及栅极，其被配置为使得所述栅极围绕所述沟道区域和所述源极区域的至少一部分。
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公开(公告)号：US08723162B2
公开(公告)日：2014-05-13
申请号：US13541022
申请日：2012-07-03
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.
摘要翻译： 纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括 从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域， 从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。
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公开(公告)号：US08722492B2
公开(公告)日：2014-05-13
申请号：US12684280
申请日：2010-01-08
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/04 , H01L29/06
CPC分类号： H01L21/047 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A method for forming a nanowire tunnel device includes forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, forming a gate structure around a channel region of the nanowire, implanting a first type of ions at a first oblique angle in a first portion of the nanowire and the first pad region, and implanting a second type of ions at a second oblique angle in a second portion of the nanowire and the second pad region.
摘要翻译： 形成纳米线隧道器件的方法包括：在半导体衬底上形成由第一衬垫区域和第二焊盘区域悬置的纳米线，在纳米线的沟道区域周围形成栅极结构，在第一斜面上注入第一类型的离子 在纳米线和第一焊盘区域的第一部分中的角度，以及在纳米线和第二焊盘区域的第二部分中以第二倾斜角度注入第二类型的离子。
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公开(公告)号：US08673699B2
公开(公告)日：2014-03-18
申请号：US13551054
申请日：2012-07-17
申请人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
发明人： Thomas N. Adam , Kangguo Cheng , Bruce B. Doris , Bala S. Haran , Pranita Kulkarni , Amlan Majumdar , Stefan Schmitz
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
摘要翻译： 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。
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公开(公告)号：US08581258B2
公开(公告)日：2013-11-12
申请号：US13277897
申请日：2011-10-20
申请人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Uday Shah , Suman Datta , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
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公开(公告)号：US08530932B2
公开(公告)日：2013-09-10
申请号：US13425654
申请日：2012-03-21
IPC分类号： H01L31/109 , H01L31/0328
CPC分类号： H01L29/7391 , H01L29/66356
摘要： A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.
摘要翻译： 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。
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公开(公告)号：US20130175597A1
公开(公告)日：2013-07-11
申请号：US13344517
申请日：2012-01-05
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译： 浮栅晶体管，存储单元及其制造方法。 浮栅晶体管包括一个或多个基本上圆柱形的选通线。 浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。 浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。 浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。
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公开(公告)号：US08445337B2
公开(公告)日：2013-05-21
申请号：US12778517
申请日：2010-05-12
IPC分类号： H01L21/00
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.
摘要翻译： 提供了一种修改具有设置在绝缘体上的半导体的晶片的方法，包括以不同的初始半导体厚度建立晶片的第一和第二区域，形成经由每个第一和第二区域上的相应纳米线通道连接的半导体焊盘对，并重塑 纳米线通道进入纳米线，每个纳米线具有反映第一和第二区域中的每一个处的不同初始半导体厚度的各自不同的厚度。
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公开(公告)号：US08343815B2
公开(公告)日：2013-01-01
申请号：US12777881
申请日：2010-05-11
IPC分类号： H01L29/72
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0895 , H01L29/402 , H01L29/42356 , H01L29/42392 , H01L29/66477 , H01L29/66977 , H01L29/7391 , H01L29/775 , H01L29/78 , H01L29/78618 , H01L29/78696 , Y10S977/723 , Y10S977/938
摘要： A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
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