公开(公告)号：US10608431B2

公开(公告)日：2020-03-31

申请号：US15794394

申请日：2017-10-26

Applicant: ANALOG DEVICES, INC.

Inventor： Linfeng He ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02 ,  H01L23/528 ,  H01L29/74 ,  G07C5/00 ,  H01L29/06

Abstract: Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

公开(公告)号：US09954356B2

公开(公告)日：2018-04-24

申请号：US14797675

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H02H9/02 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

公开(公告)号：US20170366002A1

公开(公告)日：2017-12-21

申请号：US15188626

申请日：2016-06-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

公开(公告)号：US20170243862A1

公开(公告)日：2017-08-24

申请号：US15050876

申请日：2016-02-23

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/205 ,  H01L29/872 ,  H01L27/06 ,  H01L29/778

CPC classification number: H01L29/872 ,  H01L27/0285 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1075 ,  H01L29/205 ,  H01L29/7783 ,  H01L29/8124

Abstract: Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp includes a resistor-capacitor (RC) trigger network and a metal-semiconductor field effect transistor (MESFET) clamp. The RC trigger network detects when an ESD/EOS event is present between a first node and a second node, and activates the MESFET clamp in response to detecting the ESD/EOS event. When the MESFET clamp is activated, the MESFET clamp provides a low impedance path between the first and second nodes, thereby providing ESD/EOS protection. When deactivated, the MESFET clamp provides high impedance between the first and second nodes, and thus operates with low leakage current and small static power dissipation.

公开(公告)号：US09634482B2

公开(公告)日：2017-04-25

申请号：US14335665

申请日：2014-07-18

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Sandro Herrera

IPC: H02H9/00 ,  H01L27/02 ,  H02H9/02 ,  H02H9/04

CPC classification number: H02H9/005 ,  H01L27/0285 ,  H02H9/046

Abstract: Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.

公开(公告)号：US20150115317A1

公开(公告)日：2015-04-30

申请号：US14593477

申请日：2015-01-09

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H01L21/8222

CPC classification number: H01L27/0262 ,  H01L21/8222 ,  H01L27/0259

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract translation: 提供了精密混合信号电子电路保护的装置和方法。 在一个实施例中，一种装置包括p阱，n阱，多有源二极管结构，p型有源区和n型有源区。 多极二极管结构形成在n阱上，p型有源区形成在多功能二极管结构的第一侧上的n阱中，并且n型有源区沿着 在多活性二极管结构的第二侧上的p阱和n阱的边界。 在瞬态电气事件期间，该装置被配置为提供穿过多功能二极管结构之间和之下的导电路径，以便于在n型有源区域中注入载流子。 保护装置还可以包括在p阱上形成的另一个多有源二极管结构，以进一步增强对n型有源区的载流子注入。

公开(公告)号：US08723227B2

公开(公告)日：2014-05-13

申请号：US13625611

申请日：2012-09-24

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7783

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract translation: 在第一端子和第二端子之间提供保护夹，并且包括多门高电子迁移率晶体管（HEMT），限流电路和正向触发控制电路。 多栅极HEMT包括漏极/源极，源极/漏极，第一耗尽模式（D模式）栅极，第二D模式栅极和设置在第一和第二栅极之间的增强模式（E模式）栅极 和第二D模式门。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 正向触发控制和限流电路分别耦合在E模式门和第一和第二端子之间。 当第一端子的电压通过正向触发电压超过第二端子的电压时，正向触发控制电路向E模式栅极提供激活电压。

公开(公告)号：US20140084347A1

公开(公告)日：2014-03-27

申请号：US13625577

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy ,  Shuyun Zhang

IPC: H01L27/088 ,  H01L29/778 ,  H01L21/335

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract translation: 在第一端子和第二端子之间设置包括多栅极高电子迁移率晶体管（HEMT），正向传导控制块和反向导通控制块的保护电路。 多栅极HEMT包括显式漏极/源极，第一耗尽模式（D模式）栅极，第一增强模式（E模式）栅极，第二E模式栅极，第二D模式栅极， 和明确的源/漏。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 当第一和第二端子之间的电压差大于正向传导触发电压时，正向传导控制块导通第二E模式栅极，当反向导通控制模块的电压差 比反向传导触发电压更负。

公开(公告)号：US20240363618A1

公开(公告)日：2024-10-31

申请号：US18306544

申请日：2023-04-25

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Shudong Huang ,  Yuanzhong Zhou ,  Jean-Jacques Hajjar

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Low capacitance poly-bounded silicon controlled rectifiers (SCRs) are disclosed herein. In certain embodiments, an SCR includes an n-type well (NW) and a p-type well (PW) formed adjacent to one another in a substrate. The SCR further includes active regions including p-type active (P+) fin regions over the NW and connected to an anode terminal of the SCR, and n-type active (N+) fin regions over the PW and connected to a cathode terminal of the SCR. The SCR further includes polysilicon gate regions over the PW and NW that serve to separate the active regions while also improving the SCR's turn-on speed in response to fast overstress transients.

公开(公告)号：US11942473B2

公开(公告)日：2024-03-26

申请号：US17806903

申请日：2022-06-14

Applicant: Analog Devices, Inc.

Inventor： Sirui Luo ,  Srivatsan Parthasarathy ,  Piotr Olejarz ,  Daniel Boyko ,  Ara Arakelian ,  Stuart Patterson

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H02H9/046

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.