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63 条记录 (耗时 0.026 秒)

    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials
    31.
    发明申请
    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials 有权
    图案导体，半导体和电介质材料的印刷加工

    公开(公告)号：US20090065776A1

    公开(公告)日：2009-03-12

    申请号：US12114741

    申请日：2008-05-02

    申请人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    发明人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    IPC分类号： H01L29/04 ,  C08L83/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/208

    CPC分类号： C09D5/24 ,  C09D11/101 ,  C09D11/322 ,  C09D11/36 ,  C09D11/54 ,  H01B3/02 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28008 ,  H01L27/1292 ,  H01L29/6675 ,  H01L29/78696 ,  Y10T428/24802

    摘要： Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.

    摘要翻译： 实施例涉及从含有材​​料前体的油墨印刷特征。 在一些实施例中，材料包括电活性材料，例如半导体，金属或其组合。 在另一个实施例中，该材料包括电介质。 这些实施例提供改进的印刷工艺条件，其允许更精确地控制印刷线或其它特征的形状，轮廓和尺寸。 组合物和/或方法通过增加油墨中组分的粘度和质量负载来改善对钉扎的控制。 因此，示例性方法包括在基板上以图案印刷包含材料前体和溶剂的油墨; 以图案沉淀前体以形成钉扎线; 基本上蒸发溶剂以形成由钉扎线限定的材料前体的特征; 并将材料前体转化成图案化材料。

    High k gate insulator removal
    32.
    发明授权
    High k gate insulator removal 有权
    高k栅绝缘子去除

    公开(公告)号：US07413996B2

    公开(公告)日：2008-08-19

    申请号：US10413051

    申请日：2003-04-14

    申请人： Arvind Kamath ,  Wai Lo ,  Venkatesh Gopinath

    发明人： Arvind Kamath ,  Wai Lo ,  Venkatesh Gopinath

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/31122 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.

    摘要翻译： 在基板上的集成电路中形成高k栅极绝缘层的方法。 将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。 高k层的暴露部分经受离子注入物质，其导致对高k层的暴露部分的晶格损伤。 蚀刻高K层的晶格损坏的暴露部分以留下高k栅极绝缘层。

    Methods for manufacturing RFID tags and structures formed therefrom
    33.
    发明申请
    Methods for manufacturing RFID tags and structures formed therefrom 有权
    用于制造由其形成的RFID标签和结构的方法

    公开(公告)号：US20070007342A1

    公开(公告)日：2007-01-11

    申请号：US11452108

    申请日：2006-06-12

    申请人： James Cleeves ,  J. MacKenzie ,  Arvind Kamath

    发明人： James Cleeves ,  J. MacKenzie ,  Arvind Kamath

    IPC分类号： G06K7/00 ,  G08B13/14

    CPC分类号： H01L27/1255 ,  G06K19/073 ,  G06K19/07749 ,  H01F17/0006 ,  H01L23/13 ,  H01L23/142 ,  H01L23/66 ,  H01L27/127 ,  H01L27/1292 ,  H01L28/60 ,  H01L29/66143 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/872 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.

    摘要翻译： 射频识别（RFID）标签及其制造方法。 RFID设备通常包括（1）金属天线和/或电感器; （2）其上的介电层，用于支撑和绝缘来自金属天线和/或电感器的集成电路; （3）介电层上的多个二极管和多个晶体管，二极管具有至少一个与晶体管共同的层; 和（4）与金属天线和/或电感器以及至少一些二极管电连通的多个电容器，所述多个电容器具有与所述多个二极管共同的至少一个层和/或与所述多个二极管的触点 二极管和晶体管。 该方法优选将液态含硅油墨沉积物集成到用于制造RFID电路的成本有效的集成制造工艺中。 此外，与含有机电子器件的标签相比，本RFID标签通常提供更高的性能（例如，改进的电气特性）。

    Hard mask removal
    34.
    发明申请
    Hard mask removal 有权
    硬面膜去除

    公开(公告)号：US20050006347A1

    公开(公告)日：2005-01-13

    申请号：US10615558

    申请日：2003-07-08

    申请人： Venkatesh Gopinath ,  Arvind Kamath ,  Mohammad Mirabedini ,  Ming-Yi Lee ,  Brian Baylis

    发明人： Venkatesh Gopinath ,  Arvind Kamath ,  Mohammad Mirabedini ,  Ming-Yi Lee ,  Brian Baylis

    IPC分类号： H01L21/311 ,  C23F1/00

    CPC分类号： H01L21/31144 ,  H01L21/31116

    摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

    摘要翻译： 从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层，而不会有害地蚀刻下面的层。 修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的 掩模层。

    High density memory with storage capacitor
    35.
    发明授权
    High density memory with storage capacitor 有权
    具有存储电容器的高密度存储器

    公开(公告)号：US06687114B1

    公开(公告)日：2004-02-03

    申请号：US10403433

    申请日：2003-03-31

    申请人： Arvind Kamath ,  Ruggero Castagnetti

    发明人： Arvind Kamath ,  Ruggero Castagnetti

    IPC分类号： H01G4228

    CPC分类号： H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

    摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

    摘要翻译： 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

    Diffusion barrier coated substrates and methods of making the same
    38.
    发明授权
    Diffusion barrier coated substrates and methods of making the same 有权
    扩散阻挡涂层基材及其制备方法

    公开(公告)号：US09183973B2

    公开(公告)日：2015-11-10

    申请号：US13873156

    申请日：2013-04-29

    申请人： Arvind Kamath ,  Michael Kocsis ,  Kevin McCarthy ,  Gloria Wong ,  Jiang Li

    发明人： Arvind Kamath ,  Michael Kocsis ,  Kevin McCarthy ,  Gloria Wong ,  Jiang Li

    IPC分类号： H01F5/00 ,  H01Q7/00 ,  H01L29/786 ,  H01L27/12 ,  H01Q1/22 ,  H01F41/04

    CPC分类号： H01F5/003 ,  H01F5/00 ,  H01F41/041 ,  H01L27/1218 ,  H01L27/1292 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/7869 ,  H01Q1/2283 ,  H01Q7/00

    摘要： Devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The devices include a metal substrate, a diffusion barrier layer on the metal substrate, one or more insulator layers on the diffusion barrier layer, and an antenna and/or inductor on the one or more insulator layer(s). The method includes forming a diffusion barrier layer on the metal substrate, forming one or more insulator layers on the diffusion barrier layer; and forming an antenna and/or inductor on an uppermost one of the insulator layer(s). The antenna and/or inductor is electrically connected to at least one of the diffusion barrier layer and/or the metal substrate. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into device layers formed thereon.

    摘要翻译： 公开了扩散阻挡涂层金属基板上的器件及其制造方法。 这些器件包括金属衬底，金属衬底上的扩散阻挡层，扩散阻挡层上的一个或多个绝缘体层，以及一个或多个绝缘体层上的天线和/或电感器。 该方法包括在金属基板上形成扩散阻挡层，在扩散阻挡层上形成一个或多个绝缘体层; 以及在所述绝缘体层的最上面形成天线和/或电感器。 天线和/或电感器电连接到扩散阻挡层和/或金属基底中的至少一个。 这种扩散阻挡涂层的基底防止金属原子从金属基底扩散到其上形成的器件层。

    Surveillance devices with multiple capacitors
    40.
    发明授权
    Surveillance devices with multiple capacitors 有权
    具有多个电容器的监控设备

    公开(公告)号：US08912890B2

    公开(公告)日：2014-12-16

    申请号：US13632745

    申请日：2012-10-01

    申请人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

    发明人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

    IPC分类号： H04Q5/22

    CPC分类号： H01G4/40 ,  H01G4/38

    摘要： The disclosure relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

    摘要翻译： 本公开涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。