公开(公告)号：US20070007342A1

公开(公告)日：2007-01-11

申请号：US11452108

申请日：2006-06-12

申请人： James Cleeves ,  J. MacKenzie ,  Arvind Kamath

发明人： James Cleeves ,  J. MacKenzie ,  Arvind Kamath

IPC分类号： G06K7/00 ,  G08B13/14

CPC分类号： H01L27/1255 ,  G06K19/073 ,  G06K19/07749 ,  H01F17/0006 ,  H01L23/13 ,  H01L23/142 ,  H01L23/66 ,  H01L27/127 ,  H01L27/1292 ,  H01L28/60 ,  H01L29/66143 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/872 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.

摘要翻译： 射频识别（RFID）标签及其制造方法。 RFID设备通常包括（1）金属天线和/或电感器; （2）其上的介电层，用于支撑和绝缘来自金属天线和/或电感器的集成电路; （3）介电层上的多个二极管和多个晶体管，二极管具有至少一个与晶体管共同的层; 和（4）与金属天线和/或电感器以及至少一些二极管电连通的多个电容器，所述多个电容器具有与所述多个二极管共同的至少一个层和/或与所述多个二极管的触点 二极管和晶体管。 该方法优选将液态含硅油墨沉积物集成到用于制造RFID电路的成本有效的集成制造工艺中。 此外，与含有机电子器件的标签相比，本RFID标签通常提供更高的性能（例如，改进的电气特性）。

公开(公告)号：US20080044964A1

公开(公告)日：2008-02-21

申请号：US11888949

申请日：2007-08-03

申请人： Arvind Kamath ,  James Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zurcher

发明人： Arvind Kamath ,  James Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zurcher

IPC分类号： H01L21/00 ,  H01L21/311

CPC分类号： H01L21/316 ,  H01L21/02211 ,  H01L21/02288 ,  H01L21/02318 ,  H01L21/3165 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/78621

摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

摘要翻译： 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一电介质层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

公开(公告)号：US20070287237A1

公开(公告)日：2007-12-13

申请号：US11818078

申请日：2007-06-12

申请人： Joerg Rockenberger ,  James Cleeves ,  Arvind Kamath

发明人： Joerg Rockenberger ,  James Cleeves ,  Arvind Kamath

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/7866 ,  B82Y10/00 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78681 ,  H01L29/7869

摘要： A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

摘要翻译： 一种自对准顶栅薄膜晶体管（TFT）和通过形成半导体薄膜层形成这种薄膜晶体管的方法; 在其上印刷掺杂的玻璃图案，所述掺杂玻璃图案中的间隙限定所述TFT的沟道区域; 在沟道区域上或上方形成栅电极，栅电极在其上包括栅介质膜和栅极导体; 并且将掺杂剂从掺杂的玻璃图案扩散到半导体薄膜层中。

公开(公告)号：US20050072976A1

公开(公告)日：2005-04-07

申请号：US10681509

申请日：2003-10-07

申请人： James Cleeves ,  Shuo Gu

发明人： James Cleeves ,  Shuo Gu

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L29/10

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L29/6675 ,  H01L29/78672

摘要： A method to create a polysilicon layer with large grains and uniform grain density is described. A first amorphous silicon layer is formed. A crystallizing agent is selectively introduced in a substantially symmetric pattern, preferably symmetric in two dimensions, across an area of the first amorphous layer. The crystallizing agent may be, for example, silicon nuclei, germanium, or laser energy. A mask layer is formed on the amorphous silicon layer, and holes etched in the mask layer in a symmetric pattern to expose the amorphous layer to, for example, silicon nuclei or germanium) only in the holes. The mask layer is removed and a second amorphous layer formed on the first. If laser energy is used, no mask layer or second amorphous layer is generally used. The wafer is annealed to form a polysilicon layer with substantially no amorphous silicon remaining between the grains.

摘要翻译： 描述了制造具有大晶粒和均匀晶粒密度的多晶硅层的方法。 形成第一非晶硅层。 选择性地将结晶剂以跨越第一非晶层的区域的基本上对称的图案（优选在二维对称的方式）引入。 结晶剂可以是例如硅核，锗或激光能。 在非晶硅层上形成掩模层，并且以对称图案在掩模层中蚀刻出孔，以将非晶层暴露于例如硅核或锗）仅在孔中。 除去掩模层，在第一层上形成第二非晶层。 如果使用激光能量，则通常不使用掩模层或第二非晶层。 将晶片退火以形成在晶粒之间基本上不存在无定形硅的多晶硅层。

公开(公告)号：US20050128807A1

公开(公告)日：2005-06-16

申请号：US10729865

申请日：2003-12-05

申请人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  James Cleeves

发明人： En-Hsing Chen ,  Andrew Walker ,  Roy Scheuerlein ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  James Cleeves

IPC分类号： G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427

摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

摘要翻译： 示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。 为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。 此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。 在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

公开(公告)号：US20050105371A1

公开(公告)日：2005-05-19

申请号：US10774818

申请日：2004-02-09

申请人： Mark Johnson ,  Thomas Lee ,  James Cleeves

发明人： Mark Johnson ,  Thomas Lee ,  James Cleeves

IPC分类号： G11C11/56 ,  G11C17/14 ,  G11C17/16 ,  H01L27/102 ,  G11C8/00

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

摘要翻译： 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US20050099856A1

公开(公告)日：2005-05-12

申请号：US10666971

申请日：2003-09-18

申请人： James Cleeves

发明人： James Cleeves

IPC分类号： H01L23/525 ,  H01L27/102 ,  G11C29/00

CPC分类号： H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

摘要翻译： 描述了具有限定导电线和电池的轨道堆叠的3D半导体存储器。 存储器级别成对组合，每对显示相邻级别的公共线。

公开(公告)号：US20080029901A1

公开(公告)日：2008-02-07

申请号：US11849174

申请日：2007-08-31

申请人： James Cleeves

发明人： James Cleeves

IPC分类号： H01L23/48

CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11578

摘要： A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present disclosure can be substantially the same as the minimum feature size, even at very small minimum feature size.

摘要翻译： 一种形成有利于高密度半导体器件的垂直互连的方法。 形成优选硅化钴的导电蚀刻停止层。 蚀刻停止层可以是图案化线或线的形式。 接触材料层形成在蚀刻停止层上并与蚀刻停止层接触。 图案化接触材料层以形成柱。 电介质沉积在柱之间和之间，然后将电介质平坦化以暴露柱的顶部。 柱可以用作垂直互连，其将形成在垂直互连上的下一个导电层与下面的蚀刻停止层电连接。 根据本公开形成的垂直互连的图案化尺寸可以与最小特征尺寸基本相同，即使在非常小的最小特征尺寸。

公开(公告)号：US20080022897A1

公开(公告)日：2008-01-31

申请号：US11868927

申请日：2007-10-08

申请人： Fabio Zurcher ,  Wenzhuo Guo ,  Joerg Rockenberger ,  Vladimir Dioumaev ,  Brent Ridley ,  Klaus Kunze ,  James Cleeves

发明人： Fabio Zurcher ,  Wenzhuo Guo ,  Joerg Rockenberger ,  Vladimir Dioumaev ,  Brent Ridley ,  Klaus Kunze ,  James Cleeves

IPC分类号： C09D1/00

CPC分类号： H01L21/02576 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02628

摘要： Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices. Thus, the present invention enables use of high throughput, low cost equipment and techniques for making doped semiconductor films of commercial quality and quantity from doped “liquid silicon.”

摘要翻译： 用于形成掺杂的硅烷和/或半导体薄膜的方法，用于这种方法的掺杂的液相硅烷组合物，以及掺杂的半导体薄膜和结构。 组合物在环境温度下通常是液体，并且包括IVA族原子源和掺杂剂源。 通过在其沉积的至少一部分期间照射掺杂的液体硅烷，可以在衬底上形成薄的，基本上均匀的掺杂的低聚/聚合的硅烷膜。 据信这种照射将掺杂的硅烷膜转化成相对高分子量的物质，具有相对较高的粘度和较低挥发性，通常通过交联，异构化，低聚和/或聚合。 通过掺杂的液体硅烷的照射形成的膜可以随后通过加热和退火/重结晶转化成掺杂的，氢化的非晶硅膜或适用于电子器件的掺杂的至少部分多晶的硅膜。 因此，本发明能够使用高通量，低成本的设备和技术来制造掺杂的“液态硅”具有商业质量和数量的掺杂半导体膜。

公开(公告)号：US20060232276A1

公开(公告)日：2006-10-19

申请号：US11444935

申请日：2006-05-31

申请人： James Cleeves

发明人： James Cleeves

IPC分类号： F02P17/00

CPC分类号： H01T13/467 ,  H01T13/462 ,  H01T13/50

摘要： A spark plug is disclosed having at least one main electrode and at least one secondary electrode. The gaps associated with the secondary electrodes are between one third and two thirds the optimum gap distance. Resistors associated with the secondary electrodes control the current flow and therefore the voltage on the electrodes.

摘要翻译： 公开了具有至少一个主电极和至少一个次级电极的火花塞。 与次级电极相关的间隙是最佳间隙距离的三分之一和三分之二。 与次级电极相关联的电阻器控制电流，因此控制电极上的电压。