公开(公告)号：US08877583B2

公开(公告)日：2014-11-04

申请号：US13728622

申请日：2012-12-27

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

CPC分类号： H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

摘要翻译： 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

公开(公告)号：US08835257B2

公开(公告)日：2014-09-16

申请号：US13312176

申请日：2011-12-06

申请人： Young-Pil Kim ,  Hyung-Ik Lee ,  Woo-Sung Jeon ,  Ki-Hong Kim ,  Jung-Yun Won ,  In-Sun Jung

发明人： Young-Pil Kim ,  Hyung-Ik Lee ,  Woo-Sung Jeon ,  Ki-Hong Kim ,  Jung-Yun Won ,  In-Sun Jung

IPC分类号： H01L21/762 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/1052 ,  H01L21/76224 ,  H01L27/10876

摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.

摘要翻译： 一种包括形成隔离沟槽的方法; 在隔离槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一 侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

公开(公告)号：US20120100684A1

公开(公告)日：2012-04-26

申请号：US13280430

申请日：2011-10-25

申请人： Ji-Young Min ,  Yu-Gyun Shin ,  Gab-Jin Nam ,  Young-Pil Kim

发明人： Ji-Young Min ,  Yu-Gyun Shin ,  Gab-Jin Nam ,  Young-Pil Kim

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/66545 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/165 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

摘要翻译： 制造半导体器件的方法包括在衬底上顺序地形成第一栅极绝缘层和第二栅极绝缘层，将杂质离子注入到衬底中并执行用于激活杂质离子以形成源极和漏极区域的第一热处理， 以及在第一热处理完成之后在衬底上形成第三栅极绝缘层。

公开(公告)号：US07557388B2

公开(公告)日：2009-07-07

申请号：US11398118

申请日：2006-04-05

申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC分类号： H01L31/00 ,  H01L35/26 ,  H01L31/117

CPC分类号： C30B29/06 ,  C30B15/00

摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

公开(公告)号：US20070072399A1

公开(公告)日：2007-03-29

申请号：US11530498

申请日：2006-09-11

申请人： Young-Pil Kim ,  Jin-Bum Kim ,  Jun-Ho Lee ,  Hyung-ik Lee ,  Hion-Suck Baik

发明人： Young-Pil Kim ,  Jin-Bum Kim ,  Jun-Ho Lee ,  Hyung-ik Lee ,  Hion-Suck Baik

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/36 ,  H01L31/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L31/0543 ,  Y02E10/52

摘要： Semiconductor devices are provided having a selective epitaxial growth layer that exhibits suppressed lateral growth. These semiconductor devices may include a semiconductor substrate having a silicon region, and an epitaxial growth layer formed on the silicon region. The epitaxial growth layer may comprise alternatively stacked silicon and silicon germanium epitaxial layers. The silicon germanium epitaxial layer may be thinner than the silicon epitaxial layers.

摘要翻译： 提供具有显示抑制的横向生长的选择性外延生长层的半导体器件。 这些半导体器件可以包括具有硅区域的半导体衬底和形成在硅区域上的外延生长层。 外延生长层可以包括交替堆叠的硅和锗锗外延层。 硅锗外延层可以比硅外延层薄。

公开(公告)号：US20050095857A1

公开(公告)日：2005-05-05

申请号：US10982113

申请日：2004-11-04

申请人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

发明人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC分类号： H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

摘要翻译： 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。