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    Semiconductor Devices Including Elevated Source and Drain Regions
    2.
    发明申请
    Semiconductor Devices Including Elevated Source and Drain Regions 有权
    包括高压源和排水区的半导体器件

    公开(公告)号：US20110073941A1

    公开(公告)日：2011-03-31

    申请号：US12962061

    申请日：2010-12-07

    申请人： Jin Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Methods of fabricating semiconductor devices including elevated source and drain regions
    3.
    发明授权
    Methods of fabricating semiconductor devices including elevated source and drain regions 有权
    制造包括升高的源极和漏极区域的半导体器件的方法

    公开(公告)号：US07867865B2

    公开(公告)日：2011-01-11

    申请号：US12166575

    申请日：2008-07-02

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same
    4.
    发明申请
    Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same 有权
    包括提升源和排水区的半导体器件及其制造方法

    公开(公告)号：US20090008717A1

    公开(公告)日：2009-01-08

    申请号：US12166575

    申请日：2008-07-02

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L21/336 ,  H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Semiconductor devices including elevated source and drain regions
    5.
    发明授权
    Semiconductor devices including elevated source and drain regions 有权
    半导体器件包括升高的源极和漏极区域

    公开(公告)号：US08552494B2

    公开(公告)日：2013-10-08

    申请号：US12962061

    申请日：2010-12-07

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS
    6.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS 审中-公开
    用金属半导体复合源/漏极接触区制造半导体器件的方法

    公开(公告)号：US20100197089A1

    公开(公告)日：2010-08-05

    申请号：US12699491

    申请日：2010-02-03

    申请人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.

    摘要翻译： 制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。 在晶体管上形成绝缘层并图案化以暴露源/漏区域。 在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。 在半导体源层上形成金属源层。 进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。 第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。 金属源层可以包括金属层和金属氮化物阻挡层。

    Image forming apparatus employing an electrical charge removal device with an improved configuration
    8.
    发明授权
    Image forming apparatus employing an electrical charge removal device with an improved configuration 有权
    采用具有改进结构的电荷去除装置的图像形成装置

    公开(公告)号：US08396394B2

    公开(公告)日：2013-03-12

    申请号：US12787931

    申请日：2010-05-26

    申请人： Jun-Ho Lee ,  Jeong-Yong Ju

    发明人： Jun-Ho Lee ,  Jeong-Yong Ju

    IPC分类号： G03G15/16

    CPC分类号： G03G21/06 ,  G03G15/163 ,  G03G21/1647 ,  G03G21/1661 ,  G03G21/168 ,  G03G2221/1642 ,  G03G2221/1654

    摘要： An image forming apparatus, including: a main body; an image carrying body disposed in the main body, a transfer unit and an electrical charge removal unit. The image forming apparatus forms a visible image on the image carrying body by carrying out charging, exposing and developing processes. The transfer unit transfers the visible image from the image carrying body to a printing medium. The electrical charge removal unit is configured to remove residual electrical charge from the printing medium, and is movable, in cooperation with at least one replaceable component part of the transfer unit, between an operable position at which the electrical charge removal unit is capable of removing the electrical charge from the printing medium and a non-interfering position at which the electrical charge removal unit does not interfere with the movement of the at least one replaceable component part of the transfer unit being received into or being removed from the main body for replacement.

    摘要翻译： 一种图像形成装置，包括：主体; 设置在主体中的图像承载体，转印单元和电荷去除单元。 图像形成装置通过进行充电，曝光和显影处理在图像载体上形成可见图像。 传送单元将可见图像从图像承载体传送到打印介质。 电荷去除单元被配置为从打印介质去除残留的电荷，并且可以与所述转印单元的至少一个可替换的组成部分协作地在所述电荷去除单元能够移除的可操作位置之间移动 来自打印介质的电荷和非干扰位置，在该非干扰位置，电荷消除单元不干扰转移单元的至少一个可更换部件的移动，该移动单元被接收到主体中或从主体移除以进行更换 。