公开(公告)号：US20070072399A1

公开(公告)日：2007-03-29

申请号：US11530498

申请日：2006-09-11

申请人： Young-Pil Kim ,  Jin-Bum Kim ,  Jun-Ho Lee ,  Hyung-ik Lee ,  Hion-Suck Baik

发明人： Young-Pil Kim ,  Jin-Bum Kim ,  Jun-Ho Lee ,  Hyung-ik Lee ,  Hion-Suck Baik

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/36 ,  H01L31/20

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L31/0543 ,  Y02E10/52

摘要： Semiconductor devices are provided having a selective epitaxial growth layer that exhibits suppressed lateral growth. These semiconductor devices may include a semiconductor substrate having a silicon region, and an epitaxial growth layer formed on the silicon region. The epitaxial growth layer may comprise alternatively stacked silicon and silicon germanium epitaxial layers. The silicon germanium epitaxial layer may be thinner than the silicon epitaxial layers.

摘要翻译： 提供具有显示抑制的横向生长的选择性外延生长层的半导体器件。 这些半导体器件可以包括具有硅区域的半导体衬底和形成在硅区域上的外延生长层。 外延生长层可以包括交替堆叠的硅和锗锗外延层。 硅锗外延层可以比硅外延层薄。

公开(公告)号：US08552494B2

公开(公告)日：2013-10-08

申请号：US12962061

申请日：2010-12-07

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

IPC分类号： H01L27/088

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

公开(公告)号：US07867865B2

公开(公告)日：2011-01-11

申请号：US12166575

申请日：2008-07-02

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

公开(公告)号：US20090008717A1

公开(公告)日：2009-01-08

申请号：US12166575

申请日：2008-07-02

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

公开(公告)号：US20120178231A1

公开(公告)日：2012-07-12

申请号：US13241678

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Hyung-Ik Lee ,  Ki-Hong Kim ,  Eun-Ha Lee ,  Jung-Yun Won ,  Benayad Anass

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Hyung-Ik Lee ,  Ki-Hong Kim ,  Eun-Ha Lee ,  Jung-Yun Won ,  Benayad Anass

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823807 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.

摘要翻译： 提供了制造金属硅化物层和制造具有这种金属硅化物层的半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在衬底上形成金属层，在衬底上进行第一热处理， 允许衬底和金属层与其它反应物反应以形成第一预金属硅化物层，去除金属层的未反应部分，并在衬底上进行第二热处理以将第一前金属硅化物层改变为 第二预金属硅化物层，然后熔化第二预金属硅化物层以将第二预金属硅化物层改变为金属硅化物层。

公开(公告)号：US20120135576A1

公开(公告)日：2012-05-31

申请号：US13242784

申请日：2011-09-23

申请人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

发明人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7849

摘要： Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 该方法包括提供具有沟道区的衬底; 在基板上形成包括虚拟栅极图案的栅极结构; 通过分别在栅极结构的两侧凹陷衬底来形成第一和第二沟槽; 在所述第一和第二沟槽中形成第一半导体图案; 去除伪栅极图案以暴露沟道区域的一部分; 通过使所述通道区域的所述部分凹陷来形成凹陷通道区域; 以及在凹陷区域中形成第二半导体图案。

公开(公告)号：US20080116487A1

公开(公告)日：2008-05-22

申请号：US11782237

申请日：2007-07-24

申请人： Byeong-Chan Lee ,  Si-Young Choi ,  Young-Pil Kim ,  Yong-Hoon Son ,  In-Soo Jung ,  Jin-Bum Kim

发明人： Byeong-Chan Lee ,  Si-Young Choi ,  Young-Pil Kim ,  Yong-Hoon Son ,  In-Soo Jung ,  Jin-Bum Kim

IPC分类号： H01L29/739 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/2683 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1083

摘要： Transistors having a high carrier mobility and devices incorporating the same are fabricated by forming a preliminary semiconductor layer in a semiconductor substrate at both sides of a gate pattern. A source/ drain semiconductor layer having a heterojunction with the semiconductor substrate is formed by irradiating a laser beam onto the preliminary semiconductor layer. The source/drain semiconductor layer is formed in a recrystallized single crystal structure.

摘要翻译： 具有高载流子迁移率的晶体管和其结合的器件通过在栅极图案的两侧在半导体衬底中形成初步半导体层来制造。 通过将激光束照射到初步半导体层上，形成与半导体衬底具有异质结的源/漏半导体层。 源/漏半导体层以再结晶单晶结构形成。

公开(公告)号：US08877583B2

公开(公告)日：2014-11-04

申请号：US13728622

申请日：2012-12-27

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

CPC分类号： H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

摘要翻译： 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。

公开(公告)号：US20100197089A1

公开(公告)日：2010-08-05

申请号：US12699491

申请日：2010-02-03

申请人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。 在晶体管上形成绝缘层并图案化以暴露源/漏区域。 在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。 在半导体源层上形成金属源层。 进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。 第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。 金属源层可以包括金属层和金属氮化物阻挡层。

公开(公告)号：US08586223B2

公开(公告)日：2013-11-19

申请号：US12862625

申请日：2010-08-24

申请人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

发明人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

IPC分类号： H01M6/10 ,  H01M2/02

CPC分类号： H01M10/4235 ,  H01M2/023 ,  H01M10/651 ,  H01M10/654

摘要： A secondary battery that includes a cylindrical can, an electrode assembly arranged in a jelly-role configuration within the cylindrical can and having a core extending about an axis thereof and a hollow center pin arranged within the core of the electrode assembly and having an inner diameter and an outer diameter, the outer diameter forming ones of a pair of radial lengths diametrically opposite from each other, each of said pair of radial lengths extending from the outer diameter of the center pin to an external surface of the core, wherein the sum of the pair of radial lengths is in the range of 5% to 54% of the inner diameter of the center pin.

摘要翻译： 一种二次电池，其包括圆筒形罐，电极组件，其布置在圆筒形罐内的果冻状结构中，并且具有围绕其轴线延伸的芯和布置在电极组件的芯部内的中空中心销，并且具有内径 外直径形成一对径向长度彼此直径相对的外径，所述一对径向长度从中心销的外径延伸到芯的外表面，其中， 一对径向长度在中心销的内径的5％至54％的范围内。