公开(公告)号：US08704343B2

公开(公告)日：2014-04-22

申请号：US13607677

申请日：2012-09-08

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

公开(公告)号：US20140035142A1

公开(公告)日：2014-02-06

申请号：US13562953

申请日：2012-07-31

申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Yunpeng Yin

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US20130313717A1

公开(公告)日：2013-11-28

申请号：US13479893

申请日：2012-05-24

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer.

摘要翻译： 在硬掩模层中形成线开口之后，在硬掩模层的侧壁上形成硬掩模级间隔物。 施加光刻胶并图案化以形成包括通孔开口的通孔图案。 用于印刷通孔图案的覆盖公差通过硬掩模级间隔物的横向厚度增加。 电介质材料层的一部分被图案化以通过使用硬掩模层和硬掩模级间隔件作为蚀刻掩模的蚀刻形成通孔腔图案。 随后去除硬掩模级间隔物，并且随后将该线的图案转移到电介质材料层的上部，同时通孔腔图案被转移到电介质材料层的下部。

公开(公告)号：US08569168B2

公开(公告)日：2013-10-29

申请号：US13371493

申请日：2012-02-13

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

摘要翻译： 形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

公开(公告)号：US20120329267A1

公开(公告)日：2012-12-27

申请号：US13164940

申请日：2011-06-21

申请人： David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/283

CPC分类号： G06F17/5077 ,  H01L21/76834 ,  H01L21/76885

摘要： A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

摘要翻译： 形成半导体结构的方法包括形成牺牲导电材料层。 该方法还包括在牺牲导电材料层中形成沟槽。 该方法还包括在沟槽中形成导电特征。 该方法还包括去除对导电特征有选择性的牺牲导电材料层。 该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层。

公开(公告)号：US20120074520A1

公开(公告)日：2012-03-29

申请号：US12890941

申请日：2010-09-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

摘要翻译： 使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。 双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。 通孔开口位于顶部并连接到金属层。 双镶嵌结构还包括线路开口和通孔开口内的导电特征。 电介质间隔物也存在于线路开口和通孔开口内。 介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。 在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。 因此，提供了节省空间的高编程效率电熔丝。

公开(公告)号：US08124525B1

公开(公告)日：2012-02-28

申请号：US12913143

申请日：2010-10-27

申请人： Charles W. Koburger, III ,  David V. Horak ,  Shom Pomoth ,  Chih-Chao Yang ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy

发明人： Charles W. Koburger, III ,  David V. Horak ,  Shom Pomoth ,  Chih-Chao Yang ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a method of forming local interconnect for semiconductor devices. The method includes depositing a blanket layer of conductive material over one or more semiconductor devices; creating a pattern of local interconnect covering a portion of the blanket layer of conductive material; removing rest of the blanket layer of conductive material that is not covered by the pattern of local interconnect; forming the local interconnect by the portion of the blanket layer of conductive material to connect the one or more semiconductor devices.

摘要翻译： 本发明的实施例提供一种形成用于半导体器件的局部互连的方法。 该方法包括在一个或多个半导体器件上沉积导电材料的覆盖层; 产生覆盖导电材料的覆盖层的一部分的局部互连图案; 去除未被局部互连图案覆盖的导电材料的覆盖层的其余部分; 通过导电材料的覆盖层的部分形成局部互连以连接一个或多个半导体器件。

公开(公告)号：US08482132B2

公开(公告)日：2013-07-09

申请号：US12575980

申请日：2009-10-08

申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/08121 ,  H01L2224/80001 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80359 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/82

摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.

公开(公告)号：US20120175775A1

公开(公告)日：2012-07-12

申请号：US13424651

申请日：2012-03-20

申请人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

摘要翻译： 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。

公开(公告)号：US20110193230A1

公开(公告)日：2011-08-11

申请号：US12700792

申请日：2010-02-05

申请人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Takeshi Nogami ,  Shyng-Tsong Chen ,  David V. Horak ,  Son V. Nguyen ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L24/80 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.

摘要翻译： 提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度 电介质层的表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模可以具有多个随机布置的孔。 每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。 掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。 随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。 可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。 此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。