公开(公告)号：US09935197B2

公开(公告)日：2018-04-03

申请号：US13616194

申请日：2012-09-14

Applicant: Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Hua Yu

Inventor： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Hua Yu

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7881 ,  H01L29/792

Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

公开(公告)号：US20150204041A1

公开(公告)日：2015-07-23

申请号：US14159482

申请日：2014-01-21

Applicant: Cheng-Hung Chang

Inventor： Cheng-Hung Chang

IPC: E02D1/02 ,  H04W4/00 ,  G01N21/00 ,  G01N33/24 ,  G01N7/00 ,  G01N27/02 ,  G01N33/00 ,  G01N27/416 ,  G05B15/02 ,  G01N25/56

CPC classification number: E02D1/022 ,  G01N33/004 ,  G01N33/24 ,  G01N35/00871 ,  G05B15/02 ,  H04W4/70

Abstract: A two-tier wireless soil measurement apparatus is disclosed, including a top head and a plurality of sensors, wherein top head being placed above soil surface and the plurality of sensors being scattered under soil; each sensor including a sensor housing, first communication module, sensor unit and power module; the sensor unit sensing a soil condition and generating soil data representing the soil condition, the first communication module transmitting the soil data wirelessly to top head, and the power module providing power for sensor unit and first communication module; the top head including a first communication module, controller, second communication module and power module; the first communication module receiving soil data from first communication modules of sensors, the controller processing soil data, the second communication module transmitting the soil data wirelessly to a data station, and power module providing power to first communication module, controller and second communication module.

Abstract translation: 公开了一种两层无线土壤测量装置，包括顶部头和多个传感器，其中顶部头部放置在土壤表面上方，并且多个传感器在土壤下分散; 每个传感器包括传感器壳体，第一通信模块，传感器单元和功率模块; 传感器单元感测土壤条件并产生表示土壤条件的土壤数据，第一通信模块将土壤数据无线发送到顶部头，功率模块为传感器单元和第一通信模块提供电力; 所述顶部头部包括第一通信模块，控制器，第二通信模块和电源模块; 所述第一通信模块从传感器的第一通信模块接收土壤数据，所述控制器处理土壤数据，所述第二通信模块以无线方式将土壤数据发送到数据站，以及向第一通信模块，控制器和第二通信模块提供功率的功率模块。

公开(公告)号：US08617948B2

公开(公告)日：2013-12-31

申请号：US13103594

申请日：2011-05-09

Applicant: Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

Inventor： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L29/1033 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

公开(公告)号：US08143114B2

公开(公告)日：2012-03-27

申请号：US13027436

申请日：2011-02-15

Applicant: Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

Inventor： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L2029/7858

Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Abstract translation: 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。

公开(公告)号：US07977772B2

公开(公告)日：2011-07-12

申请号：US12777937

申请日：2010-05-11

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US20100213548A1

公开(公告)日：2010-08-26

申请号：US12618505

申请日：2009-11-13

Applicant: Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Hua Yu

Inventor： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Hua Yu

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7833 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7881 ,  H01L29/792

Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

Abstract translation: 描述具有低结电容的半导体器件及其制造方法。 在一个实施例中，形成半导体器件的方法包括在衬底中形成隔离区以形成有源区。 有源区的侧壁由隔离区包围。 隔离区域被凹入以暴露有源区域的侧壁的第一部分。 有源区域的侧壁的第一部分被间隔物覆盖。 隔离区域被蚀刻以暴露有源区域的侧壁的第二部分，第二部分设置在第一部分的下方。 通过侧壁的暴露的第二部分蚀刻有源区域以形成侧向开口。 横向开口用电介质上的旋转填充。

公开(公告)号：US20100144121A1

公开(公告)日：2010-06-10

申请号：US12329279

申请日：2008-12-05

Applicant: Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L21/20 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract translation: 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20080179689A1

公开(公告)日：2008-07-31

申请号：US11669870

申请日：2007-01-31

Applicant: Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

Inventor： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC: H01L29/78 ,  H01L21/441

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/665

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract translation: 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US20060157776A1

公开(公告)日：2006-07-20

申请号：US11039159

申请日：2005-01-20

Applicant: Cheng-Hung Chang ,  Hsiao-Tzu Lu ,  Chu-Yun Fu ,  Weng Chang ,  Shwang-Ming Jeng

Inventor： Cheng-Hung Chang ,  Hsiao-Tzu Lu ,  Chu-Yun Fu ,  Weng Chang ,  Shwang-Ming Jeng

IPC: H01L29/792

CPC classification number: H01L23/3192 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer 610) protects devices on a substrate from subsequent etching operations, while a second layer (for example, a first dielectric layer 620) covers the first layer. A third layer (for example, a second dielectric layer 630) fills gaps that may be due to the topography of the devices. A fourth layer (for example, a third dielectric layer 640), brings the interlayer dielectric layer to a desired thickness and is formed using a process that yields a very flat surface completes the interlayer dielectric. Using multiple layers permit the elimination of variations (filling gaps and leveling bumps) without resorting to chemical-mechanical polishing.

Abstract translation: 提高接触模块工艺性能的系统和方法。 优选实施例包括通过减少层间电介质的表面变化来提高接触模块的工艺性能。 层间电介质包括多层，第一层（例如，接触蚀刻停止层610）保护衬底上的器件免受后续蚀刻操作，而第二层（例如，第一介电层620）覆盖第一层 层。 第三层（例如，第二介电层630）填充可能是由于器件的形貌造成的间隙。 第四层（例如，第三介电层640）使得层间电介质层达到期望的厚度并且使用产生非常平坦的表面的工艺形成来完成层间电介质。 使用多层可以消除变化（填充间隙和调平凸起），而无需采用化学机械抛光。

公开(公告)号：US20050260806A1

公开(公告)日：2005-11-24

申请号：US10849689

申请日：2004-05-19

Applicant: Cheng-Hung Chang ,  Weng Chang ,  Chu-Yun Fu

Inventor： Cheng-Hung Chang ,  Weng Chang ,  Chu-Yun Fu

IPC: H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

Abstract: Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.

Abstract translation: 包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。