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    METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE
    31.
    发明申请
    METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE 有权
    在集成电路设备中提高精细线路可靠性的方法

    公开(公告)号：US20140048927A1

    公开(公告)日：2014-02-20

    申请号：US13587998

    申请日：2012-08-17

    申请人： Chad M. Burke ,  Baozhen Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Chad M. Burke ,  Baozhen Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76847 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.

    摘要翻译： 用于形成半导体结构的结构和方法。 半导体结构包括包括至少一个铜互连层的多个层。 铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。 多个螺柱被定位在所述至少一个铜互连层内。 螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。 漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。 多个螺柱包括铜原子扩散阻挡层。

    Use of Gas Cluster Ion Beam To Reduce Metal Void Formation In Interconnect Structures
    32.
    发明申请
    Use of Gas Cluster Ion Beam To Reduce Metal Void Formation In Interconnect Structures 有权
    使用气体簇离子束减少互连结构中的金属空隙形成

    公开(公告)号：US20130113101A1

    公开(公告)日：2013-05-09

    申请号：US13290577

    申请日：2011-11-07

    申请人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Junli Wang ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L21/76804 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76865 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.

    摘要翻译： 使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。 在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。 在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。 在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。 在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

    Conductor-dielectric structure and method for fabricating
    34.
    发明授权
    Conductor-dielectric structure and method for fabricating 失效
    导体 - 电介质结构及其制造方法

    公开(公告)号：US07960276B2

    公开(公告)日：2011-06-14

    申请号：US12128713

    申请日：2008-05-29

    申请人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

    发明人： Shom Ponoth ,  David L. Rath ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

    摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

    摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

    Structure and method for dual surface orientations for CMOS transistors
    37.
    发明授权
    Structure and method for dual surface orientations for CMOS transistors 失效
    用于CMOS晶体管的双面取向的结构和方法

    公开(公告)号：US07808082B2

    公开(公告)日：2010-10-05

    申请号：US11559571

    申请日：2006-11-14

    申请人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/335

    CPC分类号： H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

    摘要： The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

    摘要翻译： 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

    Silicon on insulator devices having body-tied-to-source and methods of making
    38.
    发明授权
    Silicon on insulator devices having body-tied-to-source and methods of making 有权
    硅绝缘体器件具有身体束缚源和制造方法

    公开(公告)号：US07518191B1

    公开(公告)日：2009-04-14

    申请号：US12173280

    申请日：2008-07-15

    申请人： Thomas Dyer ,  Jack A. Mandelman ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining Sam Yang

    发明人： Thomas Dyer ,  Jack A. Mandelman ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining Sam Yang

    IPC分类号： H01L29/00

    CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/78618

    摘要： Silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a semiconductor device comprises: a gate conductor spaced above a semiconductor layer by a gate dielectric; dielectric spacers disposed laterally adjacent to sidewalls of the gate conductor; source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and a conductive implant region comprising metallic species disposed in a bottom region of the semiconductor layer for electrically connecting the source junction to the body region, wherein a drain-side of the implant region is spaced apart from the body region and a source-side of the implant region contacts the body region.

    摘要翻译： 描述了具有身体绑定到源的绝缘体上硅器件。 在一个实施例中，半导体器件包括：通过栅极电介质在半导体层之上间隔开的栅极导体; 电介质间隔件设置成横向邻近门导体的侧壁; 源极和漏极结，其横向间隔开半导体层中的体区; 以及导电植入区域，其包括设置在所述半导体层的底部区域中的金属物质，用于将所述源极接头与所述体区域电连接，其中所述植入区域的漏极侧与所述体区域间隔开，并且源极侧 植入区域接触身体区域。

    POROUS AND DENSE HYBRID INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURE
    40.
    发明申请
    POROUS AND DENSE HYBRID INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURE 失效
    多孔和渗透混合互连结构及其制造方法

    公开(公告)号：US20080122109A1

    公开(公告)日：2008-05-29

    申请号：US11458464

    申请日：2006-07-19

    申请人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

    发明人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

    摘要翻译： 一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。 该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。 半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。