公开(公告)号：US20070172984A1

公开(公告)日：2007-07-26

申请号：US11645040

申请日：2006-12-26

申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供晶片; （b）在所述晶片中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）在导电层上形成干膜; （f）用焊料填充盲孔; （g）去除干膜; （h）图案化导电层; （i）去除所述晶片的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （j）堆叠多个晶片，并进行回流处理; 和（k）切割堆叠的晶片，以便形成多个三维封装。 因此，导电层的下端插入下晶片的焊料中，以增强导电层和焊料之间的接合，并且有效地降低了连接后三维封装的整体高度。

公开(公告)号：US20070172982A1

公开(公告)日：2007-07-26

申请号：US11584546

申请日：2006-10-23

申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

公开(公告)号：US20070004087A1

公开(公告)日：2007-01-04

申请号：US11306049

申请日：2005-12-15

申请人： Jen-Chieh Kao ,  Kuo-Chung Yee

发明人： Jen-Chieh Kao ,  Kuo-Chung Yee

IPC分类号： H01L21/00

CPC分类号： H01L31/0203 ,  H01L24/94 ,  H01L27/14687 ,  H01L31/1876 ,  Y02E10/50 ,  Y02P70/521

摘要： A chip packaging process is provided. First, a matrix package substrate having a carrying surface with a plurality of scribe lines thereon is provided. The scribe lines divide the package substrate into a plurality of package substrate units. Then, a sealant is formed on each scribe line. A chip is disposed on each package substrate unit. Furthermore, the chip is electrically connected to a corresponding package substrate unit. Thereafter, a transparent cover is disposed over the matrix package substrate. The transparent cover and the matrix package substrate are connected via the sealant. After that, a trimming process along the scribe lines is performed to cut the transparent cover, the matrix package substrate and the sealant.

摘要翻译： 提供了芯片封装工艺。 首先，提供具有其上具有多个划线的承载面的矩阵封装基板。 划线将封装衬底分成多个封装衬底单元。 然后，在每个划线上形成密封剂。 芯片设置在每个封装基板单元上。 此外，芯片电连接到相应的封装衬底单元。 此后，在矩阵封装基板上设置透明盖。 透明盖和矩阵封装基板通过密封剂连接。 之后，进行沿着划线的修整处理，以切割透明盖，矩阵封装基板和密封剂。

公开(公告)号：US07002257B2

公开(公告)日：2006-02-21

申请号：US10463578

申请日：2003-06-18

申请人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao

发明人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao

IPC分类号： H01L23/28

CPC分类号： H01L27/14618 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L27/14683 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

摘要翻译： 光学部件封装包括基板，光学部件，多个间隔件，多根电线以及透明模塑料。 光学部件设置在基板上，并且使用远离基板的光学部件的表面来接收光信号。 间隔件设置在基板和光学部件之间。 电线将光学部件电连接到基板。 透明模塑料封装光学部件。 在这种情况下，每个间隔物的直径等于透明模塑料的厚度减去光学部件的厚度减去光信号进入透明模塑料之间的距离，并且光信号由 光学元件。 此外，本发明还公开了一种用于光学部件封装的封装方法。

公开(公告)号：US20050266601A1

公开(公告)日：2005-12-01

申请号：US10710696

申请日：2004-07-29

申请人： Kuo-Chung Yee ,  Chih-Lung Chen

发明人： Kuo-Chung Yee ,  Chih-Lung Chen

IPC分类号： H01L21/304 ,  H01L21/461 ,  H01L21/68

CPC分类号： H01L21/6836 ,  B81C1/00896 ,  H01L2221/68327

摘要： A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers therein such that the photoelectric devices face the dielectric layer. The spacers maintain a gap between the dielectric substrate and the wafer. Thereafter, the dielectric substrate surface away from the wafer or the wafer surface away from the dielectric substrate or both is ground. The grinding process is particularly suitable for preventing any possible damage to the photoelectric devices on a wafer.

摘要翻译： 公开了包括以下步骤的光电装置研磨过程。 提供了包括多个芯片单元的晶片。 每个芯片单元至少具有设置在表面层上的光电装置。 电介质基板用胶水附着在晶片上，其中多个间隔物在其中，使得光电器件面向电介质层。 间隔物在电介质基片和晶片之间保持间隙。 此后，离开晶片或离开电介质基片或两者的晶片表面的电介质基片表面被研磨。 研磨过程特别适用于防止对晶片上的光电装置的任何可能的损坏。

公开(公告)号：US20050176168A1

公开(公告)日：2005-08-11

申请号：US10906095

申请日：2005-02-03

申请人： Kuo-Chung Yee

发明人： Kuo-Chung Yee

IPC分类号： H01L27/14 ,  H01L21/00 ,  H01L21/56 ,  H01L23/02 ,  H01L23/12 ,  H01L27/146 ,  H01L29/18 ,  H01L29/417 ,  H04N5/335 ,  H01L33/00 ,  H04B10/12

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package structure of optical device has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires.

摘要翻译： 光学器件的封装结构具有芯片，密封剂，盖子，衬底，多个接合线和透明密封剂。 芯片具有光学器件和多个芯片连接焊盘。 密封剂设置在光学元件周围。 盖子设置在密封剂上。 衬底支撑芯片并且具有多个连接焊盘。 接合线用于将芯片的芯片连接焊盘电连接到衬底的连接焊盘。 透明密封剂形成在衬底和盖上，并封装接合线。

公开(公告)号：US20050116359A1

公开(公告)日：2005-06-02

申请号：US10904760

申请日：2004-11-26

申请人： Kuo-Chung Yee

发明人： Kuo-Chung Yee

IPC分类号： H01L23/29 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L21/565 ,  H01L23/16 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-warp package comprising a packaging substrate, a chip and a stiffening member is provided. The chip is disposed on a top surface of the packaging substrate. The stiffening member is disposed on a bottom surface of the packaging substrate in a location underneath the surrounding area of the chip. Through the disposition of a stiffening member, warping stress on the packaging substrate when the chip is encapsulated by molding compound is counterbalanced.

摘要翻译： 提供了一种包括封装基板，芯片和加强部件的抗翘曲包装。 芯片设置在封装基板的顶表面上。 加强构件在芯片的周围区域下方的位置设置在封装基板的底面上。 通过加强构件的设置，当通过模塑料封装芯片时，封装衬底上的翘曲应力是平衡的。

公开(公告)号：US20050037104A1

公开(公告)日：2005-02-17

申请号：US10710906

申请日：2004-08-12

申请人： Jen-Chieh Kao ,  Kuo-Chung Yee

发明人： Jen-Chieh Kao ,  Kuo-Chung Yee

IPC分类号： B29C45/00 ,  B29C45/14 ,  H01L21/56

CPC分类号： B29C45/0025 ,  B29C45/14639 ,  H01L21/565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

摘要翻译： 提供了一种用于模制安装在封装衬底上的半导体器件的模具。 模具包括顶模和底模。 顶部模具具有顶部流道，至少第一模拟流道和多个模具腔。 第一个虚拟跑步者与顶级跑步者相连，顶级赛跑者延伸到模具腔之间的空间。 用于容纳半导体器件的模腔连接到顶部流道。 底模具有底流道和至少第二模拟流道。 第二个虚拟跑步者与底下的跑步者相连。 第二虚拟跑步者位于上方，但是通过封装衬底与第一虚拟跑步者分离。