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    Methods of fabricating semiconductor device having a metal gate pattern
    32.
    发明授权
    Methods of fabricating semiconductor device having a metal gate pattern 有权
    制造具有金属栅极图案的半导体器件的方法

    公开(公告)号：US07772643B2

    公开(公告)日：2010-08-10

    申请号：US12457323

    申请日：2009-06-08

    申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    IPC分类号： H01L29/94 ,  H01L29/78

    CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

    摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

    摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

    Semiconductor devices including high-k dielectric materials
    33.
    发明授权
    Semiconductor devices including high-k dielectric materials 失效
    包括高k电介质材料的半导体器件

    公开(公告)号：US07696552B2

    公开(公告)日：2010-04-13

    申请号：US11227541

    申请日：2005-09-15

    申请人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    发明人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

    摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.

    摘要翻译： 半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层 层，其包括在第二导电层上的金属。 在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。 控制栅极包括掺杂有P型杂质和金属层的多晶硅层。 第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。 第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。 还公开了方法实施例。

    Methods of forming gate structures for semiconductor devices
    35.
    发明授权
    Methods of forming gate structures for semiconductor devices 有权
    形成半导体器件栅极结构的方法

    公开(公告)号：US07521316B2

    公开(公告)日：2009-04-21

    申请号：US11221062

    申请日：2005-09-07

    申请人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    发明人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28273 ,  H01L29/42324

    摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，形成绝缘衬垫。 更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极 所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。 漏电阻氧化物可以形成在第二栅电极的侧壁上。 绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。 此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。 还讨论了相关结构。

    Methods of fabricating a semiconductor device having a metal gate pattern
    36.
    发明授权
    Methods of fabricating a semiconductor device having a metal gate pattern 有权
    制造具有金属栅极图案的半导体器件的方法

    公开(公告)号：US07306996B2

    公开(公告)日：2007-12-11

    申请号：US11498197

    申请日：2006-08-03

    申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

    摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

    摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

    Methods of fabricating a semiconductor device having a metal gate pattern
    37.
    发明申请
    Methods of fabricating a semiconductor device having a metal gate pattern 有权
    制造具有金属栅极图案的半导体器件的方法

    公开(公告)号：US20060270204A1

    公开(公告)日：2006-11-30

    申请号：US11498195

    申请日：2006-08-03

    申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

    IPC分类号： H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

    摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

    摘要翻译： 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

    Methods of manufacturing a semiconductor device
    38.
    发明申请
    Methods of manufacturing a semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20060115967A1

    公开(公告)日：2006-06-01

    申请号：US11246791

    申请日：2005-10-07

    申请人： Hee-Sook Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Sun-Pil Youn ,  Woong-Hee Sohn

    发明人： Hee-Sook Park ,  Gil-Heyun Choi ,  Chang-Won Lee ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Sun-Pil Youn ,  Woong-Hee Sohn

    IPC分类号： H01L21/8238 ,  H01L21/425

    CPC分类号： H01L21/823828

    摘要： In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.

    摘要翻译： 在制造包括在氢气氛中进行热处理的多晶硅层的半导体器件的方法中，在半导体衬底上形成初步多晶硅层。 将氟（F）杂质注入到初步多晶硅层上，使得初步多晶硅层形成为多晶硅层。 在多晶硅层上进行主要的热处理，从而防止由多晶硅层中的氟（F）引起的空隙。 在主要热处理之前在多晶硅层上进一步进行辅助热处理，由此激活多晶硅层中的掺杂剂。 改善了半导体器件的电特性和性能，因为在多晶硅层中充分防止了空隙。