公开(公告)号：US06249029B1

公开(公告)日：2001-06-19

申请号：US09320595

申请日：1999-05-26

申请人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

发明人： Andres Bryant ,  William F. Clark ,  John J. Ellis-Monaghan ,  Edward P. Maciejewski ,  Edward J. Nowak ,  Wilbur D. Pricer ,  Minh H. Tong

IPC分类号： H01L2976

CPC分类号： H01L29/7841 ,  H01L27/1203

摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

摘要翻译： 用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。 本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少 漏电流。 高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层 接触基板。

公开(公告)号：US6167524A

公开(公告)日：2000-12-26

申请号：US56300

申请日：1998-04-06

申请人： Kenneth J. Goodnow ,  Michel S. Michail ,  Janak G. Patel ,  Wilbur D. Pricer ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Michel S. Michail ,  Janak G. Patel ,  Wilbur D. Pricer ,  Sebastian T. Ventrone

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F1/26 ,  G06F1/28 ,  G06F1/30

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3869 ,  Y02D10/171

摘要： An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.

摘要翻译： 一种通过动态分配系统逻辑电力来控制便携式个人计算机中的功耗的装置和方法。 计算总功耗，并将其与最佳功率效率值进行比较。 每个执行单元的预期功耗值以实际或压缩形式存储在查找表中。 如果预期的总功耗值超过功率效率值，则使所选择的执行单元无效。 相反，如果功率效率值超过预期的总功耗值，则添加执行单元功能以便保持对电池的电平电流需求。

公开(公告)号：US6130469A

公开(公告)日：2000-10-10

申请号：US66122

申请日：1998-04-24

申请人： John A. Bracchitta ,  Wilbur D. Pricer

发明人： John A. Bracchitta ,  Wilbur D. Pricer

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L23/58 ,  H01L29/04 ,  H01L29/74

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.

摘要翻译： 一种用于反熔丝结构的集成电路和制造方法，其包括设置在硅衬底中的浅沟槽氧化物隔离区域，沟槽中的氧化物具有在衬底的表面下方凹陷的顶表面，以在沟槽的每一侧形成锐角 。 衬底包括与锐角相邻的扩散区域，在扩散区域上的电绝缘层，并且电导体设置在沟槽中的凹陷氧化物上。 当电压施加在电导体上时，在尖角产生高场点，导致拐角处的电绝缘层分解，并在电导体和扩散之间产生短路，从而提供保险丝功能。

公开(公告)号：US4701642A

公开(公告)日：1987-10-20

申请号：US856889

申请日：1986-04-28

申请人： Wilbur D. Pricer

发明人： Wilbur D. Pricer

IPC分类号： H03K19/08 ,  H03K19/017 ,  H03K19/0944 ,  H03K17/04

CPC分类号： H03K19/01721 ,  H03K19/09448

摘要： A BICMOS binary logic circuit or system is provided which includes P-channel and N-channel transistors, a bipolar transistor having a base connected to the drain of the P-channel transistor, a diode, preferably a Schottky barrier diode, connected between the emitter of the bipolar transistors and the drain of the N-channel transistor, a capacitor load connected to the emitter of the bipolar transistor and an input terminal connected to control electrodes of the P-channel and N-channel transistors.

摘要翻译： 提供了一种BICMOS二进制逻辑电路或系统，其包括P沟道和N沟道晶体管，双极晶体管，其基极连接到P沟道晶体管的漏极，二极管，优选肖特基势垒二极管，连接在发射极 的双极晶体管和N沟道晶体管的漏极，连接到双极晶体管的发射极的电容器负载和连接到P沟道和N沟道晶体管的控制电极的输入端子。

公开(公告)号：US4604534A

公开(公告)日：1986-08-05

申请号：US677613

申请日：1984-12-03

申请人： Wilbur D. Pricer

发明人： Wilbur D. Pricer

IPC分类号： G11C11/409 ,  G09G5/00 ,  G11C7/06 ,  H03K5/24 ,  H03K3/287 ,  H03K3/356

CPC分类号： G11C7/065

摘要： An improved voltage sensing circuit is provided which includes a pair of cross-coupled bipolar transistors coupled to a pair of signal nodes, a pair of cross-coupled field effect transistors coupled to the same pair of signal nodes and means for activating the bipolar transistors during a first period of time and then activating the field effect transistors. The bipolar transistors are preferably NPN transistors and the field effect transistors are preferably P channel transistors. The circuit may be conveniently fabricated in complementary metal oxide semiconductor (CMOS) technology.

摘要翻译： 提供了一种改进的电压感测电路，其包括耦合到一对信号节点的一对交叉耦合双极晶体管，耦合到同一对信号节点的一对交叉耦合场效应晶体管，以及用于在双 第一时间段然后激活场效应晶体管。 双极晶体管优选为NPN晶体管，场效应晶体管优选为P沟道晶体管。 电路可以方便地用互补金属氧化物半导体（CMOS）技术制造。

公开(公告)号：US4477846A

公开(公告)日：1984-10-16

申请号：US332403

申请日：1981-12-21

申请人： Peter E. Cottrell ,  John E. Gersbach ,  Wilbur D. Pricer

发明人： Peter E. Cottrell ,  John E. Gersbach ,  Wilbur D. Pricer

IPC分类号： H03F3/343 ,  H03F3/34 ,  H03F3/347 ,  H03F3/72 ,  H03K5/02 ,  G11B5/09 ,  G11B5/02

CPC分类号： H03K5/02

摘要： This invention provides an amplifier circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The amplifier circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the amplifier without the high write voltages destroying the high performance first and second transistors.

摘要翻译： 本发明提供一种放大器电路，其具有通过对称构造的第三晶体管互连的第一和第二晶体管。 电流源选择性地连接到第三晶体管的基极。 当电流源连接到第三晶体管的基极时，第三晶体管饱和，在第一和第二晶体管之间形成非常低的阻抗路径。 然而，当电流源与第三晶体管的基极断开时，第三晶体管阻止第一和第二晶体管的基极之间的电压击穿路径。 放大器电路在改进的小型磁介质系统中特别有用，其中存储的信号和写入信号或电压都被施加到放大器的第一和第二晶体管的基极，而没有高写入电压破坏高性能的第一和第二 晶体管。

公开(公告)号：US4445201A

公开(公告)日：1984-04-24

申请号：US325697

申请日：1981-11-30

申请人： Wilbur D. Pricer

发明人： Wilbur D. Pricer

IPC分类号： G11C11/419 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

摘要： A system is provided in which two load devices connected to a latch are individually controlled and connected to a common input/output line. A bit/sense line is connected to each of two nodes on the latch. By providing two such latches each with bit/sense lines and two individually controlled load devices connected to the common input/output line, two cells of a word line may be sensed simultaneously.

摘要翻译： 提供了一种系统，其中连接到锁存器的两个负载装置被单独控制并连接到公共输入/输出线。 位/感测线连接到锁存器上的两个节点中的每一个。 通过提供两个这样的锁存器，每个具有位/检测线和连接到公共输入/输出线的两个独立控制的负载装置，可以同时感测字线的两个单元。

公开(公告)号：US4300210A

公开(公告)日：1981-11-10

申请号：US108242

申请日：1979-12-27

申请人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

发明人： Satya N. Chakravarti ,  Lawrence G. Heller ,  Wilbur D. Pricer

IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/36 ,  H03K5/08 ,  G11C27/00 ,  G11C11/24 ,  G11C11/40

CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C19/36 ,  G11C7/06

摘要： A calibrated sensing system is provided in accordance with the teachings of this invention for sensing charge in a storage medium, such as a storage capacitor, coupled to an access or bit/sense line which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor or potential well and compared with the unknown charge in the first potential to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.

摘要翻译： 根据本发明的教导，提供了一种校准的感测系统，用于感测存储介质（例如存储电容器）中的电荷，该存储介质耦合到访问或位/检测线，其补偿存储介质中的大部分变异源，并且 接入线路。 在系统中，存储在存储介质中的未知电荷经由存取线路传送到第一电容器或势阱。 将存储介质的高电荷状态写入存储介质，并且从其准备已知的分数电荷分组，将其选择性地传输到第二电容器或势阱，并与第一电位中的未知电荷进行比较，以确定第 存储在存储介质中的未知电荷。 通过选择性地使用两个或更多个电荷多级感测的分数分组。

公开(公告)号：US4287576A

公开(公告)日：1981-09-01

申请号：US134259

申请日：1980-03-26

申请人： Wilbur D. Pricer

发明人： Wilbur D. Pricer

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C11/4097 ,  G11C11/419 ,  G11C11/40

CPC分类号： G11C5/025 ,  G11C11/4097

摘要： A sense amplifying system is provided having first and second bit lines and first and second differential amplifiers arranged in tandem with a first isolation device connecting one side of the first amplifier to the first bit line and a second isolation device connecting the other side of the first amplifier to the second bit line and with a third isolation device connecting one side of the second amplifier to the first bit line and a fourth isolation device connecting the other side of the second amplifier to the second bit line. A precharging circuit charges the first and second lines to the same potential. The first amplifier is used to sense signals on the first line while using a reference voltage derived from the second line and the second amplifier is used to sense signals on the second line while using a reference voltage derived from the first word line.

摘要翻译： 提供一种感测放大系统，其具有第一和第二位线以及与将第一放大器的一侧连接到第一位线的第一隔离装置并排连接的第一和第二差分放大器;以及第二隔离装置， 放大器到第二位线，以及将第二放大器的一侧连接到第一位线的第三隔离器件和将第二放大器的另一侧连接到第二位线的第四隔离器件。 预充电电路将第一和第二线路充电到相同的电位。 第一放大器用于感测第一行上的信号，同时使用从第二行导出的参考电压，并且第二放大器用于在使用从第一字线导出的参考电压的同时检测第二行上的信号。

公开(公告)号：US06604174B1

公开(公告)日：2003-08-05

申请号：US09709872

申请日：2000-11-10

申请人： Alvar A. Dean ,  Kenneth J. Goodnow ,  Stephen W. Mahin ,  Wilbur D. Pricer ,  Dana J. Thygesen ,  Sebastian T. Ventrone

发明人： Alvar A. Dean ,  Kenneth J. Goodnow ,  Stephen W. Mahin ,  Wilbur D. Pricer ,  Dana J. Thygesen ,  Sebastian T. Ventrone

IPC分类号： G06F1200

CPC分类号： G06F12/0853 ,  G06F12/0844 ,  G06F12/0846

摘要： The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport cache. Therefore, multiple processes, which could be processors, tasks, or threads can access the cache during any cycle. Moreover, the ways of the cache can be allocated to the different processes and then dynamically reallocated based on performance. Most preferably, a relational cache miss percentage is used to reallocate the ways, but other metrics may also be used.

摘要翻译： 本发明提供了一种用于动态分配统一多端口高速缓存的基于性能的系统和方法。 公开了一种多端口缓存系统，其允许通过多端口标签的多个单周期查找和来自多端口高速缓存的多个单周期高速缓存访​​问。 因此，可能是处理器，任务或线程的多个进程可以在任何周期内访问高速缓存。 此外，缓存的方式可以分配给不同的进程，然后基于性能动态重新分配。 最优选地，使用关系高速缓存未命中百分比来重新分配方式，但也可以使用其他度量。