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60 条记录 (耗时 0.019 秒)

    Electrically programmable anti-fuse circuit
    1.
    发明授权
    Electrically programmable anti-fuse circuit 失效
    电子可编程反熔丝电路

    公开(公告)号：US6020777A

    公开(公告)日：2000-02-01

    申请号：US938754

    申请日：1997-09-26

    申请人： John A. Bracchitta ,  Wilbur D. Pricer

    发明人： John A. Bracchitta ,  Wilbur D. Pricer

    IPC分类号： G11C17/16 ,  H01H37/76

    CPC分类号： G11C17/16

    摘要： An array of anti-fuse cells forming rows and columns of a matrix is described. The anti-fuse cell includes an MOS capacitor connected to a source of high voltage which is capable of rendering the capacitor permanently conductive. A first voltage limiting transistor connects the free end of the MOS capacitor to a second transistor. An address decoder provides address signals to a source and gate of the second transistor within the cell. The MOS capacitor is rendered permanently conductive when the first and second transistors are rendered conductive. The high voltage is confined to the MOS capacitor, which is fused through the high current being drawn through the capacitor by the first and second transistors. Other components on the integrated circuit carrying the array of fusible cells are maintained free of any high voltage.

    摘要翻译： 描述形成矩阵行和列的反熔丝单元的阵列。 反熔丝单元包括连接到能够使电容器永久导电的高电压源的MOS电容器。 第一电压限制晶体管将MOS电容器的自由端连接到第二晶体管。 地址解码器向单元内的第二晶体管的源极和栅极提供地址信号。 当第一和第二晶体管导通时，MOS电容器被永久导通。 高电压被限制在MOS电容器中，MOS电容器通过第一和第二晶体管通过电容器吸收的高电流熔断。 携带易熔电池阵列的集成电路上的其他部件保持不受任何高电压的影响。

    Electrically alterable antifuse using FET
    3.
    发明授权
    Electrically alterable antifuse using FET 失效
    使用FET的电可变反熔丝

    公开(公告)号：US6130469A

    公开(公告)日：2000-10-10

    申请号：US66122

    申请日：1998-04-24

    申请人： John A. Bracchitta ,  Wilbur D. Pricer

    发明人： John A. Bracchitta ,  Wilbur D. Pricer

    IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L23/58 ,  H01L29/04 ,  H01L29/74

    CPC分类号： H01L23/5252 ,  H01L2924/0002

    摘要： An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.

    摘要翻译： 一种用于反熔丝结构的集成电路和制造方法，其包括设置在硅衬底中的浅沟槽氧化物隔离区域，沟槽中的氧化物具有在衬底的表面下方凹陷的顶表面，以在沟槽的每一侧形成锐角 。 衬底包括与锐角相邻的扩散区域，在扩散区域上的电绝缘层，并且电导体设置在沟槽中的凹陷氧化物上。 当电压施加在电导体上时，在尖角产生高场点，导致拐角处的电绝缘层分解，并在电导体和扩散之间产生短路，从而提供保险丝功能。

    Low-power critical error rate communications controller
    7.
    发明授权
    Low-power critical error rate communications controller 失效
    低功率关键错误率通信控制器

    公开(公告)号：US06802033B1

    公开(公告)日：2004-10-05

    申请号：US09286855

    申请日：1999-04-06

    申请人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Claude L. Bertin ,  Alvar A. Dean ,  Kenneth J. Goodnow ,  Scott W. Gould ,  Patrick E. Perry ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： G06F1100

    CPC分类号： G06F11/10 ,  H04L1/0053

    摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

    摘要翻译： 一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。 当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。 低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。 选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。 或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

    Integrated high-performance decoupling capacitor and heat sink
    9.
    发明授权
    Integrated high-performance decoupling capacitor and heat sink 失效
    集成高性能去耦电容和散热片

    公开(公告)号：US06548338B2

    公开(公告)日：2003-04-15

    申请号：US09764504

    申请日：2001-01-17

    申请人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

    发明人： Kerry Bernstein ,  Robert M. Geffken ,  Wilbur D. Pricer ,  Anthony K. Stamper ,  Steven H. Voldman

    IPC分类号： H01L218238

    CPC分类号： H01L28/40 ,  H01L23/3672 ,  H01L23/3735 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

    摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

    摘要翻译： 一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。 因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

    Method and apparatus for allocating data and instructions within a shared cache
    10.
    发明授权
    Method and apparatus for allocating data and instructions within a shared cache 失效
    用于在共享缓存内分配数据和指令的方法和装置

    公开(公告)号：US06532520B1

    公开(公告)日：2003-03-11

    申请号：US09394965

    申请日：1999-09-10

    申请人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

    发明人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

    IPC分类号： G06F1200

    CPC分类号： G06F12/121 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/6042

    摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.

    摘要翻译： 提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。 高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。 然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。 替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。 用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态 第一预定计数。 耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。