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80 条记录 (耗时 0.035 秒)

    System and method for communicating command parameters between a processor and a memory flow controller
    31.
    发明申请
    System and method for communicating command parameters between a processor and a memory flow controller 失效
    用于在处理器和存储器流控制器之间传送命令参数的系统和方法

    公开(公告)号：US20070079018A1

    公开(公告)日：2007-04-05

    申请号：US11207986

    申请日：2005-08-19

    申请人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Todd Swanson ,  Thuong Truong

    发明人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Todd Swanson ,  Thuong Truong

    IPC分类号： G06F13/00

    CPC分类号： G06F13/32 ,  G06F13/1642

    摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

    摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

    System and method for communicating with a processor event facility
    32.
    发明申请
    System and method for communicating with a processor event facility 失效
    与处理器事件设施通信的系统和方法

    公开(公告)号：US20070043936A1

    公开(公告)日：2007-02-22

    申请号：US11207971

    申请日：2005-08-19

    申请人： Michael Day ,  Charles Johns ,  John Liberty ,  Todd Swanson

    发明人： Michael Day ,  Charles Johns ,  John Liberty ,  Todd Swanson

    IPC分类号： G06F7/38

    CPC分类号： G06F13/24

    摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

    摘要翻译： 提供了一种用于与处理器事件设施进行通信的系统和方法。 系统和方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
    37.
    发明申请
    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
    非对称异构多处理器环境中的内存障碍原语

    公开(公告)号：US20060026309A1

    公开(公告)日：2006-02-02

    申请号：US10902474

    申请日：2004-07-29

    申请人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Day ,  Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

    摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

    Enhancement of real-time operating system functionality using a hypervisor
    38.
    发明申请
    Enhancement of real-time operating system functionality using a hypervisor 审中-公开
    使用管理程序增强实时操作系统功能

    公开(公告)号：US20050251806A1

    公开(公告)日：2005-11-10

    申请号：US10842281

    申请日：2004-05-10

    申请人： Marc Auslander ,  Boas Betzler ,  Dilma Da Silva ,  Michael Day ,  Orran Krieger ,  Paul McKenney ,  Michal Ostrowski ,  Bryan Rosenburg ,  Robert Wisniewski ,  James Xenidis

    发明人： Marc Auslander ,  Boas Betzler ,  Dilma Da Silva ,  Michael Day ,  Orran Krieger ,  Paul McKenney ,  Michal Ostrowski ,  Bryan Rosenburg ,  Robert Wisniewski ,  James Xenidis

    IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F9/48

    CPC分类号： G06F9/4812 ,  G06F9/45533 ,  G06F9/4881

    摘要： A system, method and computer program product for enhancing a real-time operating system (RTOS) with functionality normally associated with a general purpose operating system (GPOS). A hypervisor that is adapted to perform a real-time scheduling function supports concurrent execution of an RTOS and a GPOS on a system of shared hardware resources. The RTOS or its applications can utilize services provided by the GPOS. Such services may include one or more of file system organization, network communication, network management, database management, security, user-interface support and others. To enhance operational robustness and security, the hypervisor can be placed in read-only storage while maintaining the ability to update scheduling mechanisms. A programmable policy manager that is maintained in read-write storage can be used to dictate scheduling policy changes to the hypervisor as required to accommodate current needs.

    摘要翻译： 一种用于增强具有通常与通用操作系统（GPOS）相关联的功能的实时操作系统（RTOS）的系统，方法和计算机程序产品。 适用于执行实时调度功能的虚拟机管理程序支持共享硬件资源系统上的RTOS和GPOS的并发执行。 RTOS或其应用程序可以利用GPOS提供的服务。 这样的服务可以包括文件系统组织，网络通信，网络管理，数据库管理，安全性，用户界面支持等中的一个或多个。 为了增强运营的鲁棒性和安全性，管理程序可以放置在只读存储中，同时保持更新调度机制的能力。 维护在读写存储器中的可编程策略管理器可用于根据需要来规定对管理程序的调度策略更改以适应当前需求。

    Methods and apparatus for efficient multi-tasking
    39.
    发明申请
    Methods and apparatus for efficient multi-tasking 审中-公开
    高效多任务的方法和设备

    公开(公告)号：US20050120185A1

    公开(公告)日：2005-06-02

    申请号：US10725129

    申请日：2003-12-01

    申请人： Takeshi Yamazaki ,  Michael Day ,  Thuong Truong

    发明人： Takeshi Yamazaki ,  Michael Day ,  Thuong Truong

    IPC分类号： G06F15/167 ,  G06F1/32 ,  G06F9/46 ,  G06F9/52 ,  G06F12/14 ,  G06F12/16 ,  G06F13/28

    CPC分类号： G06F9/52 ,  G06F1/3203 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/522 ,  G06F9/544

    摘要： A system includes a shared memory; a memory interface unit coupled to the shared memory and operable to retrieve data from the shared memory at requested addresses, and to write data to the shared memory at requested addresses; and a plurality of processing units in communication with the memory interface and operable to (i) instruct the memory interface unit that data be loaded with reservation from the shared memory at a specified address such that any operations may be performed on the data, and (ii) instruct the memory interface unit that the data be stored in the shared memory at the specified address, wherein at least one of the processing units includes a status register having one or more bits indicating whether a reservation was lost: whether the data at the specified address in shared memory was modified.

    摘要翻译： 系统包括共享存储器; 存储器接口单元，其耦合到共享存储器并且可操作以在所请求的地址处从共享存储器检索数据，并且以请求的地址将数据写入共享存储器; 以及多个处理单元，与所述存储器接口通信，并且可操作以（i）以指定的地址指示所述存储器接口单元从所述共享存储器预先加载所述数据，使得可以对所述数据执行任何操作，并且（ ii）指示存储器接口单元将数据存储在共享存储器中的指定地址处，其中至少一个处理单元包括状态寄存器，该状态寄存器具有一个或多个位，表示预留是否丢失： 共享内存中的指定地址已修改。

    Software-controlled cache set management
    40.
    发明申请
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US20050055507A1

    公开(公告)日：2005-03-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

    摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。