公开(公告)号：US20090269918A1

公开(公告)日：2009-10-29

申请号：US12111122

申请日：2008-04-28

申请人： Yi Ma ,  Robert Bertram Ogle

发明人： Yi Ma ,  Robert Bertram Ogle

IPC分类号： H01L21/28 ,  H01L21/311

CPC分类号： H01L21/324 ,  H01L21/3247 ,  H01L27/11568 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7854 ,  H01L29/792

摘要： Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

摘要翻译： 公开了制造具有平滑侧壁和圆角顶角和边缘的半导体FIN结构的方法。 一种方法包括形成多个半导体FIN结构。 在多个半导体FIN结构的顶表面和侧壁表面上形成牺牲氧化物层，用于使多个半导体FIN结构的顶表面和侧壁表面之间的角和边缘倒圆。 用高选择性氧化物蚀刻剂除去牺牲氧化物层。 多个半导体FIN结构在氢环境中退火。 在多个半导体FIN结构上形成隧道氧化物。

公开(公告)号：US20090152617A1

公开(公告)日：2009-06-18

申请号：US11957787

申请日：2007-12-17

申请人： Yi Ma ,  Robert Ogle

发明人： Yi Ma ,  Robert Ogle

IPC分类号： H01L29/792 ,  H01L21/31

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7923

摘要： Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher than a k-value of an nth charge storage layer; n-1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers.

摘要翻译： 提供了包含用于存储单元的异质结构可变富硅氮化物的电荷存储堆，以及用于制造电荷存储堆的方法。 电荷存储堆可以包含半导体衬底上的第一绝缘层; n在第一绝缘层上形成包括富硅氮化物的存储层，其中电荷存储层的数量从底部增加到顶部，并且第n-1个电荷存储层的k值高于k值 的第n电荷存储层; n-1个电介质层，其在n个电荷存储层中的每一个之间包含基本上化学计量的氮化硅; 以及第n电荷存储层上的第二绝缘层。

公开(公告)号：US20090042353A1

公开(公告)日：2009-02-12

申请号：US11836299

申请日：2007-08-09

申请人： Yi Ma ,  Philip Allan Kraus ,  Christopher Sean Olsen ,  Khaled Z. Ahmed ,  Abhilash J. Mayur

发明人： Yi Ma ,  Philip Allan Kraus ,  Christopher Sean Olsen ,  Khaled Z. Ahmed ,  Abhilash J. Mayur

IPC分类号： H01L21/331

CPC分类号： B23K26/0738 ,  B23K26/082 ,  B23K26/0876 ,  H01L21/268 ,  H01L29/665

摘要： Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.

摘要翻译： 通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。 在源 - 漏区和栅电极上沉积镍的贱金属层，然后沉积具有比镍更高的熔融温度的金属的上覆层。 此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅电极的顶表面处形成金属硅化物接触。 该方法还包括去除剩余的含金属层，然后在激光退火之前在衬底上沉积光吸收层。

公开(公告)号：US07081419B2

公开(公告)日：2006-07-25

申请号：US10847789

申请日：2004-05-18

申请人： Yuan Chen ,  Feng Li ,  Yi Ma ,  Kurt G. Steiner

发明人： Yuan Chen ,  Feng Li ,  Yi Ma ,  Kurt G. Steiner

IPC分类号： H01L21/31

CPC分类号： H01L21/28202 ,  H01L29/513

摘要： The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.

摘要翻译： 本发明提供一种能够显着延迟半导体器件内的硼渗透的半导体器件及其制造方法。 在本发明中，半导体器件包括位于半导体晶片的衬底之上的栅极电介质，其中栅极电介质包括氮化层和电介质层。 本发明还包括位于介电层和氮化层之间的氮化过渡区域和位于栅极电介质上方的栅极。

公开(公告)号：US07078302B2

公开(公告)日：2006-07-18

申请号：US10784904

申请日：2004-02-23

申请人： Yi Ma ,  Khaled Z. Ahmed ,  Kevin L. Cunningham ,  Robert C. McIntosh ,  Abhilash J. Mayur ,  Haifan Liang ,  Mark Yam ,  Toi Yue Becky Leung ,  Christopher Olsen ,  Shulin Wang ,  Majeed Foad ,  Gary Eugene Miner

发明人： Yi Ma ,  Khaled Z. Ahmed ,  Kevin L. Cunningham ,  Robert C. McIntosh ,  Abhilash J. Mayur ,  Haifan Liang ,  Mark Yam ,  Toi Yue Becky Leung ,  Christopher Olsen ,  Shulin Wang ,  Majeed Foad ,  Gary Eugene Miner

IPC分类号： H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/268 ,  H01L21/28035 ,  H01L21/324

摘要： In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.

摘要翻译： 在一个实施例中，本发明通常提供了一种用于退火衬底上的掺杂层的方法，包括将多晶层沉积到栅极氧化物层并用掺杂剂注入多晶层以形成掺杂的多晶层。 该方法还包括将掺杂多晶层暴露于快速热退火以便容易地将掺杂剂分布在整个多晶层中。 随后，该方法包括将掺杂多晶层暴露于激光退火以激活多晶层上部的掺杂剂。

公开(公告)号：US20060062917A1

公开(公告)日：2006-03-23

申请号：US11223896

申请日：2005-09-09

申请人： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

发明人： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

IPC分类号： C23C16/00

CPC分类号： C23C16/308 ,  C23C16/401 ,  C23C16/56

摘要： In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.

摘要翻译： 在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地 将衬底暴露于后沉积退火，氮化工艺和热退火工艺。 在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。 在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。

公开(公告)号：US20050186765A1

公开(公告)日：2005-08-25

申请号：US10784904

申请日：2004-02-23

申请人： Yi Ma ,  Khaled Ahmed ,  Kevin Cunningham ,  Robert McIntosh ,  Abhilash Mayur ,  Haifan Liang ,  Mark Yam ,  Toi Leung ,  Christopher Olsen ,  Shulin Wang ,  Majeed Foad ,  Gary Miner

发明人： Yi Ma ,  Khaled Ahmed ,  Kevin Cunningham ,  Robert McIntosh ,  Abhilash Mayur ,  Haifan Liang ,  Mark Yam ,  Toi Leung ,  Christopher Olsen ,  Shulin Wang ,  Majeed Foad ,  Gary Miner

IPC分类号： H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L21/36 ,  C30B1/00 ,  H01L21/20 ,  H01L21/425 ,  H01L21/44

CPC分类号： H01L21/268 ,  H01L21/28035 ,  H01L21/324

摘要： In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.

摘要翻译： 在一个实施例中，本发明通常提供了一种用于退火衬底上的掺杂层的方法，包括将多晶层沉积到栅极氧化物层并用掺杂剂注入多晶层以形成掺杂的多晶层。 该方法还包括将掺杂多晶层暴露于快速热退火以便容易地将掺杂剂分布在整个多晶层中。 随后，该方法包括将掺杂多晶层暴露于激光退火以激活多晶层上部的掺杂剂。

公开(公告)号：US06506673B2

公开(公告)日：2003-01-14

申请号：US09878690

申请日：2001-06-11

申请人： Yi Ma ,  Huili Shao ,  Joseph A. Taylor ,  Allen Yen

发明人： Yi Ma ,  Huili Shao ,  Joseph A. Taylor ,  Allen Yen

IPC分类号： H01L214763

CPC分类号： H01L29/66545

摘要： The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.

摘要翻译： 本发明提供了一种方法，其包括在半导体衬底上限定包括玻璃上的旋转玻璃的虚拟栅极结构，在所述虚拟栅极结构上形成介电层，去除所述伪栅极结构以在所述电介质层内形成栅极开口，以及形成 栅极材料，其在栅极开口内包括金属。

公开(公告)号：US06313007B1

公开(公告)日：2001-11-06

申请号：US09589816

申请日：2000-06-07

申请人： Yi Ma ,  Scott F. Shive ,  Melissa M. Brown

发明人： Yi Ma ,  Scott F. Shive ,  Melissa M. Brown

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A trench isolation structure is fabricated using high pressure and low temperature. A substrate is provided within which a trench is formed. The trench walls are annealed in nitrogen at a pressure above atmospheric pressure to remove silicon damage caused by plasma etching. The exposed side walls of the trench are oxidized at a pressure above atmospheric pressure to form an oxidized layer. The trench is filled with an oxide. Optionally, re-oxidation densification may be performed at a pressure above atmospheric pressure and a temperature in the range of about 600° C. to about 800° C.

摘要翻译： 使用高压和低温制造沟槽隔离结构。 提供其中形成沟槽的衬底。 沟槽壁在氮气中在高于大气压力的压力下退火，以消除由等离子体蚀刻引起的硅损伤。 沟槽的暴露侧壁在高于大气压的压力下被氧化以形成氧化层。 沟槽填充有氧化物。 任选地，可以在高于大气压的压力和约600℃至约800℃范围内的温度下进行再氧化致密化。

公开(公告)号：US06235560B1

公开(公告)日：2001-05-22

申请号：US09375150

申请日：1999-08-16

申请人： Yi Ma ,  Allen Yen

发明人： Yi Ma ,  Allen Yen

IPC分类号： H01L2100

CPC分类号： H01L29/66477 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/66545

摘要： A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.

摘要翻译： 一种制造晶体管的方法包括以下步骤：提供包括硅 - 锗外延层的硅衬底，在硅 - 锗外延层的沟道区上形成掩模注入层，以及将掺杂剂注入到硅 - 锗外延层中，使用 所述掩模注入层限定与所述沟道区相邻的间隔开的源极和漏极区。 该方法还包括在植入之后去除掩模注入层以暴露沟道区的步骤。 在暴露的沟道区上形成硅外延层，并且将硅外延层的至少一部分转换为氧化硅以限定晶体管的栅极电介质层。 栅极介电层包括栅极氧化物层和栅极氧化物层与沟道区之间的硅保护层。 导电栅极形成在栅极氧化物层的上表面上。 由于栅极介质层不包括锗，所以为高速硅 - 锗晶体管提供稳定的栅介质层。