公开(公告)号：US07205185B2

公开(公告)日：2007-04-17

申请号：US10663471

申请日：2003-09-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US06803315B2

公开(公告)日：2004-10-12

申请号：US10212938

申请日：2002-08-05

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21302

CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.

摘要翻译： 提供了一种用于阻挡来自FET器件的栅电极的植入物的方法。 形成覆盖基板和栅极电极堆叠的第一平坦化膜。 第一平面化膜通过抛光或自平面平坦化。 为了通过HDP沉积或者在材料上使用旋涂，该膜是自平面化的。 在需要抛光的情况下，第一平面化膜通过抛光进行平坦化，直到栅电极的顶部露出。 在第一平面化膜的上表面的水平面下方蚀刻栅电极。 然后沉积第二平坦化膜和抛光剂的覆盖层以将其平坦化至暴露第一平坦化膜的水平，将第二平坦化膜形成为覆盖栅极顶表面的注入块。 取下第一个平面化膜。 通过使用注入块将掺杂剂注入衬底来形成反向掺杂区域，以阻止掺杂剂注入到栅电极中。 注入块在植入反向掺杂区域期间保护FET的栅电极免受不希望的注入杂质。 第一平面化膜由选自HDP（高密度等离子体）氧化硅和HDP氮化硅的材料，包含ONO的层间介电层材料和光致抗蚀剂组成。 栅电极由选自多晶硅和金属的材料组成。 第二平面化膜包括诸如HDP氧化物，HDP氮化物和包括ARC的有机层的材料。 第二平面化膜包括与第一平坦化膜不同的材料。

公开(公告)号：US07960790B2

公开(公告)日：2011-06-14

申请号：US12119765

申请日：2008-05-13

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanararyan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanararyan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US06833569B2

公开(公告)日：2004-12-21

申请号：US10328234

申请日：2002-12-23

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

IPC分类号： H01L27148

CPC分类号： H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

摘要： The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

摘要翻译： 本发明提供一种用于制造具有与前门对准的背栅的平面DGFET的方法。 本发明的方法通过在后门的一部分中产生载流子耗尽区来实现该对准。 载流子耗尽区减小了源极/漏极区域和后栅极之间的电容，从而提供了高性能自对准平面双栅极场效应晶体管（DGFET）。 本发明还提供一种具有与前门对准的后门的平面DGFET。 通过在后门的部分中提供载流子耗尽区来实现前到后栅极对准。

公开(公告)号：US06812105B1

公开(公告)日：2004-11-02

申请号：US10604382

申请日：2003-07-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2255 ,  H01L29/6656 ,  H01L29/78621

摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.

摘要翻译： 用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

公开(公告)号：US06657244B1

公开(公告)日：2003-12-02

申请号：US10195596

申请日：2002-06-28

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Robert J. Purtell

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Robert J. Purtell

IPC分类号： H01L2976

CPC分类号： H01L29/66507 ,  H01L29/66545

摘要： A method of fabricating a semiconductor structure where a low gate resistance is obtained, while simultaneously reducing silicon consumption in the source/drain diffusion regions. The method provides a semiconductor structure having a thin silicide region formed atop source/drain regions and a thicker silicide region formed atop gate regions. The method includes: first forming a structure which includes self-aligned silicide regions atop the source/drain diffusion regions and the gate region. A non-reactive film and a planarizing film are then applied to the structure containing the self-aligned silicide regions and thereafter a thicker silicide region, as compared to the self-aligned silicide region located atop the source/drain regions, is formed on the gate region.

摘要翻译： 一种制造半导体结构的方法，其中获得低栅极电阻，同时降低源极/漏极扩散区域中的硅消耗。 该方法提供了半导体结构，其具有形成在源极/漏极区顶部的薄硅化物区域和形成在栅极区域顶部的较厚硅化物区域。 该方法包括：首先在源极/漏极扩散区域和栅极区域顶部形成包括自对准硅化物区域的结构。 然后将非反应性膜和平坦化膜施加到包含自对准硅化物区域的结构，然后与位于源极/漏极区域顶部的自对准硅化物区域相比较，形成较厚的硅化物区域 门区域。

公开(公告)号：US06586289B1

公开(公告)日：2003-07-01

申请号：US09882250

申请日：2001-06-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L218238

CPC分类号： H01L21/823425 ,  H01L21/82345

摘要： A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film. The inventive structure contains a non-conformal film formed on both horizontal and vertical surfaces of a structure including at least non-predoped patterned gate regions.

摘要翻译： 提供了用于改善金属氧化物半导体场效应晶体管（MOSFET）结构的栅激活的方法和结构。 本发明的方法包括以下步骤：在栅极电介质材料层的顶部形成具有多个图案化栅极叠层的结构; 在包括多个图案化的栅叠层的结构上形成非保形膜; 用第一抗蚀剂阻挡多个图案化栅极堆叠中的一些，同时留下所述多个未封装的其它图案化栅极堆叠; 将第一离子注入未封闭的图案化栅极堆叠中; 去除第一抗蚀剂并用第二抗蚀剂阻挡先前未封闭的图案化栅叠层; 将第二离子注入未被第二抗蚀剂阻挡的图案化栅极堆叠中; 并除去第二抗蚀剂和非保形膜。 本发明的结构包含形成在包括至少非预制图案化栅极区域的结构的水平和垂直表面上的非保形膜。

公开(公告)号：US06531365B2

公开(公告)日：2003-03-11

申请号：US09888160

申请日：2001-06-22

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Peter Smeys ,  Isabel Y. Yang

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Peter Smeys ,  Isabel Y. Yang

IPC分类号： H01L21336

CPC分类号： H01L21/82345

摘要： A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a first planarizing organic film on the gate dielectric material and abutting vertical sidewalls of the patterned gate stacks, said planarizing organic film not being present on top, horizontal surfaces of each of the patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and first planarizing organic film and forming a second planarizing organic film and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by said second resist; and removing the second resist and the second planarizing organic film.

摘要翻译： 提供了一种用于改善金属氧化物半导体场效应晶体管（MOSFET）结构的栅激活的方法。 本发明的方法包括以下步骤：在栅极电介质材料层的上方形成多个图案化的栅叠层; 在所述栅极电介质材料上形成第一平面化有机膜并邻接所述图案化栅极叠层的垂直侧壁，所述平面化有机膜不存在于每个所述图案化栅极堆叠的顶部水平表面上; 用第一抗蚀剂阻挡多个图案化栅极堆叠中的一些，同时留下所述多个未封装的其它图案化栅极堆叠; 将第一离子注入未封闭的图案化栅极堆叠中; 去除第一抗蚀剂和第一平面化有机膜并形成第二平面化有机膜并用第二抗蚀剂阻挡先前未封闭的图案化栅叠层; 将第二离子注入未被所述第二抗蚀剂阻挡的图案化栅极堆叠中; 并除去第二抗蚀剂和第二平面化有机膜。

公开(公告)号：US06642147B2

公开(公告)日：2003-11-04

申请号：US09938097

申请日：2001-08-23

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Michael P. Belyansky

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Michael P. Belyansky

IPC分类号： H01L21302

CPC分类号： H01L21/76819 ,  H01L21/31056

摘要： Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.

公开(公告)号：US07436029B2

公开(公告)日：2008-10-14

申请号：US11867271

申请日：2007-10-04

申请人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Suk Hoon Ku

发明人： Bruce B. Doris ,  Dureseti Chidambarrao ,  Suk Hoon Ku

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823864 ,  H01L29/7843 ,  Y10S257/90 ,  Y10S438/938

摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.

摘要翻译： 半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，第一场效应晶体管包括具有第一宽度的间隔物，第二场效应晶体管包括具有第二宽度的压缩间隔物，第一宽度不同于所述第一宽度 第二宽度。 优选地，第一宽度比第二宽度窄。 拉伸应力介电膜在晶体管上形成阻挡蚀刻停止层。