公开(公告)号：US20080042798A1

公开(公告)日：2008-02-21

申请号：US11848263

申请日：2007-08-31

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

公开(公告)号：US20070229212A1

公开(公告)日：2007-10-04

申请号：US11758746

申请日：2007-06-06

申请人： Arne Ballantine ,  Cyril Cabral ,  Daniel Edelstein ,  Anthony Stamper

发明人： Arne Ballantine ,  Cyril Cabral ,  Daniel Edelstein ,  Anthony Stamper

IPC分类号： H01C10/00

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/242 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49105

摘要： An electrical structure. The electrical structure includes a resistor having a length L and an electrical resistance R(t) at a time t; and a laser radiation directed onto a portion of the resistor, wherein the portion of the resistor includes a fraction F of the length L, wherein the laser radiation heats the portion of the resistor such that the electrical resistance R(t) instantaneously changes at a rate dR/dt, and wherein the resistor is coupled to a semiconductor substrate.

摘要翻译： 电气结构。 电气结构包括在时间t具有长度L和电阻R（t）的电阻器; 以及引导到电阻器的一部分的激光辐射，其中电阻器的该部分包括长度为L的分数F，其中激光辐射加热电阻器的部分，使得电阻R（t）瞬时变化 速率dR / dt，并且其中所述电阻器耦合到半导体衬底。

公开(公告)号：US20070187800A1

公开(公告)日：2007-08-16

申请号：US11737304

申请日：2007-04-19

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01C17/267

摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

公开(公告)号：US20070123015A1

公开(公告)日：2007-05-31

申请号：US11164634

申请日：2005-11-30

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Jeffrey Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony Stamper

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Jeffrey Johnson ,  Jonghae Kim ,  Jean-Olivier Plouchart ,  Anthony Stamper

IPC分类号： H01L27/12 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

摘要翻译： 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US20070122957A1

公开(公告)日：2007-05-31

申请号：US11164651

申请日：2005-11-30

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US20070065966A1

公开(公告)日：2007-03-22

申请号：US11162661

申请日：2005-09-19

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L29/84

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US20060292863A1

公开(公告)日：2006-12-28

申请号：US11160465

申请日：2005-06-24

申请人： Jeffrey Gambino ,  Anthony Stamper

发明人： Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76865

摘要： Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered chamber. An at least partially sacrificial encapsulation layer is then formed on the exposed metal surface in the tool to prevent reaction of the exposed metal surface with the ambient. Exposure of the metal is thereby prevented.

摘要翻译： 公开了用于在半导体加工期间防止金属暴露的金属封装的方法。 在一个实施例中，该方法包括在露出开口底部的金属表面的结构中形成开口，其中开口形成步骤发生在包括至少一个聚集室的工具中。 然后在工具中的暴露的金属表面上形成至少部分牺牲的封装层，以防止暴露的金属表面与环境的反应。 从而防止了金属的暴露。

公开(公告)号：US20060189137A1

公开(公告)日：2006-08-24

申请号：US10906552

申请日：2005-02-24

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Gambino ,  Anthony Stamper

IPC分类号： H01L21/302 ,  H01L23/48 ,  H01L29/40 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device, and the device so formed. Depositing a low dielectric constant material on a substrate. Depositing a hard mask on the low dielectric constant material. Forming an at least one first feature within the low dielectric constant material and the hard mask. Depositing a conformal liner over the hard mask and within the at least one feature, wherein the liner occupies more than at least 2% of a volume of the at least one feature, and wherein a thickness of the liner is at least approximately ⅓ a minimum width of the at least one feature. Metallizing the at least one feature.

摘要翻译： 形成半导体器件的方法和如此形成的器件。 在基板上沉积低介电常数材料。 在低介电常数材料上沉积硬掩模。 在低介电常数材料和硬掩模内形成至少一个第一特征。 在所述硬掩模上并且在所述至少一个特征内沉积保形衬垫，其中所述衬垫占据所述至少一个特征的体积的至少2％，并且其中所述衬垫的厚度为至少约1/3 所述至少一个特征的最小宽度。 金属化至少一个特征。

公开(公告)号：US20060166486A1

公开(公告)日：2006-07-27

申请号：US11391050

申请日：2006-03-28

申请人： Anthony Stamper

发明人： Anthony Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

摘要： A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

摘要翻译： 一种形成半导体器件的方法。 沉积第一和第二介电材料的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层中形成第一个特征。 选择性地蚀刻电介质材料的交替层以去除具有第一介电材料的每个层中的第一介电材料的至少一部分，并使第二介电材料基本上未被蚀刻。

公开(公告)号：US20050233478A1

公开(公告)日：2005-10-20

申请号：US10709109

申请日：2004-04-14

申请人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L23/525 ,  H01L27/08 ,  H01P3/08

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。