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31.发明授权公开(公告)号：US08533436B2
公开(公告)日：2013-09-10
申请号：US12492652
申请日：2009-06-26
Applicant: Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
Inventor： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
CPC classification number: G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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公开(公告)号：US20100005474A1
公开(公告)日：2010-01-07
申请号：US12380210
申请日：2009-02-25
Applicant: Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit. In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.
Abstract translation: 一种促进计算机系统或集成电路内多个时钟域之间确定性的技术。 在一个实施例中，一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。
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公开(公告)号：US20090222654A1
公开(公告)日：2009-09-03
申请号：US12220092
申请日：2008-07-22
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。
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34.发明授权Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection 失效具有源操作数有效位的指令的推测调度，以及在目的地操作数无效位检测上重新调度公开(公告)号：US06925550B2
公开(公告)日：2005-08-02
申请号：US10040223
申请日：2002-01-02
Applicant: Eric Sprangle , Michael J. Haertel , David J. Sager
Inventor： Eric Sprangle , Michael J. Haertel , David J. Sager
IPC: G06F9/38
CPC classification number: G06F9/3861 , G06F9/3836 , G06F9/3842 , G06F9/3857
Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.
Abstract translation: 一种在包括至少一个源寄存器的处理器中执行数据推测指令的方法和装置，每个源寄存器包括用于指示所述至少一个源寄存器中的数据的有效性的位。 数据有效性电路，耦合到所述一个或多个源寄存器，以确定所述源寄存器中的数据的有效性，以及基于所述至少一个源寄存器中的有效位来指示目的地寄存器中的数据的有效性。 处理器可选地包括检查单元，以从执行单元中退出那些将有效数据写入到目的地寄存器的指令，并重新安排将无效数据写入目的地寄存器的执行指令。
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公开(公告)号：US09792115B2
公开(公告)日：2017-10-17
申请号：US13976997
申请日：2011-12-23
Applicant: Jesus Corbal , Andrew T. Forsyth , Thomas D. Fletcher , Lisa K. Wu , Eric Sprangle
Inventor： Jesus Corbal , Andrew T. Forsyth , Thomas D. Fletcher , Lisa K. Wu , Eric Sprangle
CPC classification number: G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
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Patent Agency Ranking
公开(公告)号：US20140149717A1
公开(公告)日：2014-05-29
申请号：US14169491
申请日：2014-01-31
Applicant: Eric Sprangle
Inventor： Eric Sprangle
IPC: G06F9/30
CPC classification number: G06F9/3001 , G06F9/30036 , G06F9/30145 , G06F9/3893
Abstract: In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有多个执行单元的处理器，其中至少一个包括具有包括多个乘法器和加法器的乘法累积（MAC）单元的电路，并且执行用户级乘法 - 累加 指令，用多个元素填充目标存储器，每个元素对应于像素块的像素的绝对值。 描述和要求保护其他实施例。
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公开(公告)号：US20130179661A1
公开(公告)日：2013-07-11
申请号：US13783963
申请日：2013-03-04
Applicant: Eric Sprangle
Inventor： Eric Sprangle
IPC: G06F9/30
CPC classification number: G06F9/3001 , G06F9/30036 , G06F9/30145 , G06F9/3893
Abstract: In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有多个执行单元的处理器，其中至少一个包括具有包括多个乘法器和加法器的乘法累积（MAC）单元的电路，并且执行用户级乘法 - 累加 指令，用多个元素填充目标存储器，每个元素对应于像素块的像素的绝对值。 描述和要求保护其他实施例。
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公开(公告)号：US20090248990A1
公开(公告)日：2009-10-01
申请号：US12059193
申请日：2008-03-31
Applicant: Eric Sprangle
Inventor： Eric Sprangle
CPC classification number: G06T1/20 , G06F3/0644 , G06F9/30043 , G06F9/3867 , G06F9/5016
Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.
Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。
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公开(公告)号：US08930722B2
公开(公告)日：2015-01-06
申请号：US12380210
申请日：2009-02-25
Applicant: Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
Abstract translation: 公开了在多个不对称处理元件之间控制功率和处理的技术。 在一个实施例中，一个或多个非对称处理元件被功率管理以根据系统的性能和功率需求在多个处理元件之间迁移进程或线程。
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公开(公告)号：US20140078159A1
公开(公告)日：2014-03-20
申请号：US14085778
申请日：2013-11-20
Applicant: Eric Sprangle , Matt Craighead , Chris Goodman , Belliappa Kuttanna
Inventor： Eric Sprangle , Matt Craighead , Chris Goodman , Belliappa Kuttanna
IPC: G06T1/20
CPC classification number: G06T1/20
Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.
Abstract translation: 一种共享执行资源的技术。 在一个实施例中，CPU和GPU根据工作负载，功率注意事项或可用资源通过在CPU和GPU之间调度或传送指令和信息来共享资源。
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