公开(公告)号：US20190051565A1

公开(公告)日：2019-02-14

申请号：US15673519

申请日：2017-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees ,  Thorsten Kammler

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor (CMOS) device comprising an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region is provided, that comprises: depositing a raised source and drain (RSD) layer of a first type in the NMOS region and the PMOS region at the same time; selectively removing the RSD layer of the first type in one of the NMOS region and the PMOS region; and depositing an RSD layer of a second type in the one of the NMOS region and the PMOS region.

公开(公告)号：US20190043764A1

公开(公告)日：2019-02-07

申请号：US15667017

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Gunter Grasshoff

IPC: H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

公开(公告)号：US10157774B1

公开(公告)日：2018-12-18

申请号：US15658570

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Carsten K. Peters ,  Peter Baars

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/485

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact scheme for landing on different contact area levels of a semiconductor structure and methods of manufacture. The structure includes a first contact at a first level of the structure; a jumper contact at a second, upper level of the structure; an etch stop layer having an opening over the first contact and partially encapsulating the jumper contact with an opening exposing the jumper contact; and contacts in electrical contact with the first contact at the first level and the jumper contact at the second, upper level, through the openings.

公开(公告)号：US20170317108A1

公开(公告)日：2017-11-02

申请号：US15645686

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L49/02 ,  H01L27/108 ,  H01L27/06 ,  H01L21/84 ,  H01L21/762 ,  H01L21/265 ,  H01L29/94 ,  H01L21/285

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09735174B2

公开(公告)日：2017-08-15

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/265 ,  H01L21/285 ,  H01L21/84 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/786 ,  H01L27/06 ,  H01L29/94

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

公开(公告)号：US20160307926A1

公开(公告)日：2016-10-20

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

Abstract translation: 公开了一种集成电路产品，其包括SOI结构，其包括体半导体衬底，位于体半导体衬底上的掩埋绝缘层和位于绝缘层上的半导体层，其中在SOI结构的第一区域中，半导体层 并且去除了掩埋绝缘层，并且在SOI结构的第二区域中，半导体层和掩埋绝缘层存在于体半导体衬底之上。 该产品还包括半导体本体器件，其包括位于第一区域中的体半导体衬底上的第一栅极结构和包括位于第二区域中的半导体层上的第二栅极结构的SOI半导体器件，其中第一和第二栅极结构 具有基本上延伸到体半导体衬底的上表面上方的共同高度水平的最终栅极高度。

公开(公告)号：US20160204129A1

公开(公告)日：2016-07-14

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H01L27/108 ,  H01L21/265 ,  H01L21/285 ,  H01L29/786 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：提供包括衬底的SOI晶片，在衬底上形成的掩埋氧化物（BOX）层和形成在BOX层上的半导体层，去除半导体 在所述晶片的第一区域中，以暴露所述BOX层，在所述第一区域中的暴露的BOX层上形成介电层，并在所述介电层上形成导电层。 此外，提供了包括形成在晶片上的电容器的半导体器件，其中电容器包括包括晶片的掺杂半导体衬底的第一电容器电极，包括晶片的超薄BOX层的电容器绝缘体和高k 形成在超薄BOX层上的电介质层，以及包含形成在高k电介质层上的导电层的第二电容器电极。

公开(公告)号：US09349842B2

公开(公告)日：2016-05-24

申请号：US13793645

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L27/115 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L21/823462 ,  H01L27/11509 ,  H01L29/516 ,  H01L29/78391

Abstract: Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure.

Abstract translation: 可以在氧化铪的基础上形成诸如场效应晶体管或电容器的铁电电路元件，其也可以在制造快速晶体管的复杂高k金属栅电极结构期间使用。 为此，可以在任何合适的制造阶段对具有适当厚度和材料组成的铪基氧化物进行图案化，而不会不利地影响用于制造复杂的高k金属栅电极结构的整个工艺流程。

公开(公告)号：US20160111549A1

公开(公告)日：2016-04-21

申请号：US14812245

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

Abstract translation: 本公开提供了形成半导体电路元件和半导体电路元件的方法，其中半导体电路元件包括具有设置在半导体衬底的第一有源区上的第一栅极结构的第一半导体器件和具有第二半导体元件的第二半导体器件 栅极结构设置在所述半导体衬底的第二有源区上方，所述第一栅极结构包括在栅极电极材料形成在所述铁电材料上之前被埋入所述第一有源区中的铁电材料，并且所述第二栅极结构包括高k材料不同 来自铁电材料。

公开(公告)号：US20150187660A1

公开(公告)日：2015-07-02

申请号：US14143362

申请日：2013-12-30

Applicant: Globalfoundries Inc.

Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同的掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。