公开(公告)号：US20050280072A1

公开(公告)日：2005-12-22

申请号：US11216263

申请日：2005-08-31

申请人： Giovanni Naso ,  Elio D'Ambrosio

发明人： Giovanni Naso ,  Elio D'Ambrosio

IPC分类号： G11C29/14 ,  G11C29/46 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105 ,  H01L29/76

CPC分类号： G11C29/46 ,  G11C16/04 ,  G11C29/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

公开(公告)号：US09030870B2

公开(公告)日：2015-05-12

申请号：US13219439

申请日：2011-08-26

申请人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

发明人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

摘要翻译： 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

公开(公告)号：US07738310B2

公开(公告)日：2010-06-15

申请号：US12032928

申请日：2008-02-18

申请人： Giovanni Naso ,  Stefano Donnola

发明人： Giovanni Naso ,  Stefano Donnola

IPC分类号： G11C17/18 ,  G11C17/00 ,  H01L7/00 ,  H01H85/00

CPC分类号： G11C17/18

摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit.

摘要翻译： 本公开的一个或多个实施例提供了用于操作具有熔丝电路的存储器件的方法，装置和系统。 一种方法实施例包括检测指示在多个熔丝电路中的至少一个的操作期间使用的电压是否已经达到阈值电平的信号，响应于检测到电压已达到阈值而初始化多个熔丝电路中的至少一个 至少部分地响应于所述至少一个初始化熔丝电路的输出的检测到的状态改变来读取所述多个熔丝电路中的至少一个的输出。

公开(公告)号：US07565587B2

公开(公告)日：2009-07-21

申请号：US11519415

申请日：2006-09-12

申请人： Giuliano Gennaro Imondi ,  Giovanni Naso

发明人： Giuliano Gennaro Imondi ,  Giovanni Naso

IPC分类号： G11C29/00

CPC分类号： G11C16/3445 ,  G11C16/344

摘要： Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.

摘要翻译： 操作存储器件的存储器件和方法在擦除验证操作期间提供使用不同的电位，便于正常擦除操作和随后的擦除检查操作。 与普通擦除操作相比，这种装置和方法便于使用缩写的过程随后检查擦除的存储器单元的数据增益。

公开(公告)号：US07254756B2

公开(公告)日：2007-08-07

申请号：US10696971

申请日：2003-10-30

申请人： Giovanni Naso

发明人： Giovanni Naso

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G11C29/02 ,  G11C29/40

摘要： A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first series combination compares the values in the predetermined bit position to determine if they are all a logical zero. A second series combination of bit match circuits compares the same predetermined bit position in the data words. The second series combination compares the values to determine if they are all a logical one. If either condition is true, the value of the bit is output through an output buffer. If both conditions are false, the output buffer is placed in a high impedance state to indicate an error condition exists in that bit position.

摘要翻译： 位匹配电路的第一串联组合比较了压缩操作中涉及的数据字中的预定位位置。 第一系列组合比较预定位位置中的值，以确定它们是否都是逻辑零。 位匹配电路的第二串联组合比较数据字中相同的预定位位置。 第二个系列组合比较这些值，以确定它们是否都是逻辑的。 如果任一条件为真，则通过输出缓冲区输出该位的值。 如果两个条件均为假，则输出缓冲器处于高阻抗状态，以指示该位位置存在错误条件。

公开(公告)号：US20060044880A1

公开(公告)日：2006-03-02

申请号：US11127810

申请日：2005-05-12

申请人： Giovanni Naso

发明人： Giovanni Naso

IPC分类号： G11C7/10

CPC分类号： G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.

摘要翻译： 具有正常操作模式和测试操作模式的存储器件在质量程序中是有用的。 测试操作模式包括具有多于一个压缩级别的数据压缩测试模式。 读取和验证重复测试模式所需的时间可以减少，因为仅需要读取存储器件的单词的一小部分以确定存储器件准确地写入和存储数据值的能力。 选择性地禁用输出，如果一组单词的一个单词的位位置具有与多个单词组的单词的任何剩余单词不同的数据值。

公开(公告)号：US06917545B2

公开(公告)日：2005-07-12

申请号：US10367587

申请日：2003-02-14

申请人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

发明人： Girolamo Gallo ,  Giuliano Gennaro Imondi ,  Giovanni Naso ,  Tommaso Vali

IPC分类号： G11C7/10 ,  G11C16/04

CPC分类号： G11C7/106 ,  G11C7/1021 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1066

摘要： A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The resulting architecture effectively doubles throughput without increasing memory device latency.

摘要翻译： 包括突发体系结构的存储器件的方法和装置采用双总线结构，其双倍的时钟速率复用到输出总线上。 所产生的架构有效地增加了吞吐量，而不会增加内存设备的延迟。

公开(公告)号：US20130058164A1

公开(公告)日：2013-03-07

申请号：US13563314

申请日：2012-07-31

申请人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

发明人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

公开(公告)号：US07934048B2

公开(公告)日：2011-04-26

申请号：US12619364

申请日：2009-11-16

申请人： Giovanni Naso ,  Stefano Donnola

发明人： Giovanni Naso ,  Stefano Donnola

IPC分类号： G06F12/00

CPC分类号： G06F13/16 ,  Y02D10/14

摘要： In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

摘要翻译： 在各种实施例中，装置和系统以及方法可以包括增强型寄存器以向存储器阵列提供致动器信号，增强型寄存器包括第一存储器件，其包括第一使能输入，耦合到寄存器数据的第一数据输入 输入和第一存储器件输出，第一存储器件输出以耦合到存储器阵列，并且增强寄存器以包括第二存储器件，其包括第二使能输入，耦合到寄存器数据输入的第二数据输入和第二存储器 存储器件输出，其中第二存储器件输出提供指示何时来自第一存储器件输出的一个或多个致动器信号将被耦合到寄存器数据输入的第一输出信号。

公开(公告)号：US20100064188A1

公开(公告)日：2010-03-11

申请号：US12619364

申请日：2009-11-16

申请人： Giovanni Naso ,  Stefano Donnola

发明人： Giovanni Naso ,  Stefano Donnola

IPC分类号： G06F11/267

CPC分类号： G06F13/16 ,  Y02D10/14

摘要： In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

摘要翻译： 在各种实施例中，装置和系统以及方法可以包括增强型寄存器以向存储器阵列提供致动器信号，增强型寄存器包括第一存储器件，其包括第一使能输入，耦合到寄存器数据的第一数据输入 输入和第一存储器件输出，第一存储器件输出以耦合到存储器阵列，并且增强寄存器以包括第二存储器件，其包括第二使能输入，耦合到寄存器数据输入的第二数据输入和第二存储器 存储器件输出，其中第二存储器件输出提供指示何时来自第一存储器件输出的一个或多个致动器信号将被耦合到寄存器数据输入的第一输出信号。