公开(公告)号：US20190067905A1

公开(公告)日：2019-02-28

申请号：US15692136

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Ellis-Monaghan ,  Sebastian Ventrone ,  Vibhor Jain ,  Yves Ngu

IPC: H01S5/062 ,  H01S5/00 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S5/223 ,  H01S5/22

Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

公开(公告)号：US10211090B2

公开(公告)日：2019-02-19

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L23/482 ,  H01L23/31

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US10121884B2

公开(公告)日：2018-11-06

申请号：US15806532

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/8249 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/737 ,  H01L29/66 ,  H01L21/8226 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L29/732 ,  H03F3/213

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

公开(公告)号：US20180286968A1

公开(公告)日：2018-10-04

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

CPC classification number: H01L29/732 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US10014397B1

公开(公告)日：2018-07-03

申请号：US15383171

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  David L. Harame ,  Renata Camillo-Castillo

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/417 ,  H01L21/265 ,  H01L29/735 ,  H01L27/12

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

公开(公告)号：US09859382B2

公开(公告)日：2018-01-02

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L25/065 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/737

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US20170365695A1

公开(公告)日：2017-12-21

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/8228 ,  H01L21/8226 ,  H01L29/04 ,  H03F3/213 ,  H01L21/8222 ,  H01L29/165 ,  H01L29/161 ,  H01L27/082 ,  H01L29/66

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US09847408B1

公开(公告)日：2017-12-19

申请号：US15187860

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L21/8222 ,  H03F3/213 ,  H01L21/8226

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

公开(公告)号：US09825157B1

公开(公告)日：2017-11-21

申请号：US15196920

申请日：2016-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata A. Camillo-Castillo ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor with a stress component and methods of manufacture. The heterojunction bipolar transistor includes a collector region, an emitter region and a base region. Stress material is formed within a trench of a substrate and surrounding at least the collector region and the base region.

公开(公告)号：US20170162656A1

公开(公告)日：2017-06-08

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L29/737 ,  H01L29/161 ,  H01L27/092 ,  H01L25/065 ,  H01L29/20

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.