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    In situ transposition
    31.
    发明授权
    In situ transposition 有权

    公开(公告)号：US10698975B2

    公开(公告)日：2020-06-30

    申请号：US16063793

    申请日：2016-01-27

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Naveen Muralimanohar ,  Benjamin Feinberg ,  John Paul Strachan

    IPC: G06F17/16 ,  G11C13/00 ,  G06G7/16 ,  G11C7/16

    Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

    Adjustable Precision for Multi-Stage Compute Processes
    33.
    发明申请
    Adjustable Precision for Multi-Stage Compute Processes 审中-公开

    公开(公告)号：US20200042287A1

    公开(公告)日：2020-02-06

    申请号：US16052218

    申请日：2018-08-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  Sergey Serebryakov ,  John Paul Strachan

    IPC: G06F7/483 ,  G06N3/063 ,  G06N3/08

    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.

    Hash computation using memristor-implemented dot product engine
    34.
    发明授权
    Hash computation using memristor-implemented dot product engine 有权

    公开(公告)号：US10419346B1

    公开(公告)日：2019-09-17

    申请号：US15966719

    申请日：2018-04-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： John Paul Strachan ,  Catherine Graves ,  Suhas Kumar

    IPC: H04L9/06 ,  G06F17/16 ,  H04L29/06 ,  H04L12/743 ,  G11C11/16

    Abstract: An input string is mapped to a vector of input voltages. The vector is applied to input rows of a dot product engine having memristor elements at intersections of the input rows and output columns. A hash of the input string is determined based on output of the dot product engine as to which the vector of input voltages have been applied to the input rows thereof. An output column may be selected from output voltages of the columns, and the hash determined from the selected column. The output voltage of a column is equal to a sum of a product of the input voltage in each input row and a value of the memristor element at the intersection of the input row and the column. The hash can be used within a filtering technique applied to the input string, such as in the context of network security.

    Nonvolatile memory cross-bar array
    37.
    发明授权
    Nonvolatile memory cross-bar array 有权

    公开(公告)号：US10319441B2

    公开(公告)日：2019-06-11

    申请号：US16220647

    申请日：2018-12-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/04 ,  G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    NONVOLATILE MEMORY CROSS-BAR ARRAY
    38.
    发明申请
    NONVOLATILE MEMORY CROSS-BAR ARRAY 审中-公开

    公开(公告)号：US20190139605A1

    公开(公告)日：2019-05-09

    申请号：US16220647

    申请日：2018-12-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second sat of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

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