公开(公告)号：US20050164431A1

公开(公告)日：2005-07-28

申请号：US11072779

申请日：2005-03-04

申请人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

发明人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

摘要翻译： 本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。 该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。 在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。 这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

公开(公告)号：US07535066B2

公开(公告)日：2009-05-19

申请号：US10349686

申请日：2003-01-23

申请人： Antonio L. P. Rotondaro ,  Luigi Colombo ,  Mark R. Visokay ,  Rajesh Khamankar ,  Douglas E. Mercer

发明人： Antonio L. P. Rotondaro ,  Luigi Colombo ,  Mark R. Visokay ,  Rajesh Khamankar ,  Douglas E. Mercer

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

摘要翻译： 一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

公开(公告)号：US07402524B2

公开(公告)日：2008-07-22

申请号：US11292883

申请日：2005-12-02

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L21/00

CPC分类号： H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化 在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

公开(公告)号：US20060183337A1

公开(公告)日：2006-08-17

申请号：US11343680

申请日：2006-01-31

申请人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

发明人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC分类号： H01L21/302 ,  C23F1/00 ,  B44C1/22

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

公开(公告)号：US20060084229A1

公开(公告)日：2006-04-20

申请号：US11292883

申请日：2005-12-02

申请人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

发明人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC分类号： H01L21/8234

CPC分类号： H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

公开(公告)号：US20050156286A1

公开(公告)日：2005-07-21

申请号：US11038545

申请日：2005-01-18

申请人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477 ,  H01L23/58

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US06869862B2

公开(公告)日：2005-03-22

申请号：US10637288

申请日：2003-08-08

申请人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01I21/46 ,  H01L21/479 ,  H01I21/326 ,  H01I21/78

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US07560792B2

公开(公告)日：2009-07-14

申请号：US11626624

申请日：2007-01-24

申请人： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

发明人： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

IPC分类号： H01L27/105

CPC分类号： H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

摘要翻译： 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质层上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

公开(公告)号：US07183165B2

公开(公告)日：2007-02-27

申请号：US10702234

申请日：2003-11-06

申请人： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

发明人： Rajesh Khamankar ,  Douglas T. Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James J. Chambers

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

摘要翻译： 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质层上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

公开(公告)号：US06730566B2

公开(公告)日：2004-05-04

申请号：US10264729

申请日：2002-10-04

申请人： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

发明人： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  Y10S438/92

摘要： A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.

摘要翻译： 提供了用于高压晶体管器件的非热氮化栅极形成的方法。 非热氮化栅极形成可用于双厚度栅极电介质结构的形成。 非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。 栅极电介质层的氮化破坏了栅极电介质层的表面。 通过相对较低温度的再氧化工艺去除栅介电层的受损表面。 低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。